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Testing times for system developers

The creation of a system test standard remains 'work in progress'. By Graham Pitcher.

Boundary scan or JTAG, a technique embodied in IEEE1149.1, has been used for quite some time to examine the performance of individual chips and some of the boards on which they reside. Yet the approach has failed to progress very much beyond that. With growing system complexity, you might well have expected a similar standard to have evolved, but it hasn't.

However, the industry isn't ignoring the issue. Since 2005, the System JTAG Working Group (SJTAG) has been looking at how to bring IEEE1149.1 style functionality to the world of systems. But, according to SJTAG chair Ian McIntosh: "Initially, the scope was to find a way to extend JTAG to systems. When I took over as chair, I had in my mind that it would take less than nine months before we could submit a project authorisation request (PAR) to IEEE. But here we are seven years later."

In McIntosh's opinion, it's a reflection on the scale of the problem. "We're now taking a step back and focusing on identifying the core elements. Can we do it all in one standard or can we define a manageable core which can be taken through to a standard reasonably quickly? Then, we could develop extensions on a .1 and .2 basis to deal with the 'corner cases'."

One of the problems is that existing standards continue to develop and new ones emerge. "1149.1 was updated in 2013, adding extensions which deal with some of the issues we're addressing. But it still doesn't do everything we want. Meanwhile, P1687 has brought in embedded instruments and we have to think about how we deal with this. All these issues are part of what SJTAG is trying to address."

McIntosh is well aware of the potential benefits of an industry wide system level test procedure; his day job is a testability lead with Selex ES in Glasgow. He asked: "How can we develop tests that can be used at the board level and in manufacture which can then be repurposed, with minimal effort, for reuse at the system level?"

His definition of 'system' is concise. "It's any kind of aggregated system of boards – but system test is different to manufacturing test, which is looking at assembly defects. With system test, you're dealing with boards which have passed tests, so we need to examine things like post manufacturing flaws and field reprogrammability."

Another issue is that JTAG has minimal dependency on functioning hardware. "You can still use JTAG to test a board that won't power up," he noted, adding "boundary scan is structural test."

Field reprogrammability is said by McIntosh to be a 'big issue' for Selex. "The last thing we want to do is to remove the radar system from the nose of an aircraft in order to load new software."

He highlighted the issues being addressed by SJTAG. "With a chip, there's a limited number of things you need to look at. Boards are more complex, but at the system level, there are issues around how those boards interact. You're also bringing in boards that you haven't designed. How do you deal with that?"

Part of the problem here is that companies may not want to hand over design information for reasons of confidentiality. "So we need to find a way to import essential data without asking board vendors to share what they might see as vital information."

One of the issues on the SJTAG agenda is dealing with multiple boards in a system. "How do you get to the individual boards?" McIntosh pondered. "A scan chain is presented at the board's edge, but when you have multiple boards, you need an architecture that gives you access from the system's boundaries. It might need a test connector, for example, and this will need chain management to allow you to find your way to a particular board.

"These are the kinds of thing which need to be dealt with and it may be that extensions will be needed to a core standard."

He also realises that cost is an issue. "We could put a gateway on each board, but that adds cost. COTS chips could also help, but different companies will deal with the issues in different ways."

Built in self test is another potential competitor. "The BA-BIST (board assisted BIST) project from iNEMI was looking at what device vendors could do to make BIST usable as part of board level test. The activity concluded at Phase 3," McIntosh said, "but I believe a Phase 4 was being considered, based on some of the issues raised by SJTAG."

One potential solution is to house SJTAG related functionality on a system's motherboard. "But that's a trade off," McIntosh admitted. "Companies might not want to house active components on a motherboard because if it fails, it will be more difficult to replace."

So, 10 years into the development process, where does McIntosh see SJTAG now? "We have made several steps forward, but we're having to take a few steps backward in order to review where we are. We have identified hundreds of things that may need to be addressed, but need to reduce that to a handful of essentials that enable the rest.

"With things like P1687 coming along, we also have to think ahead and not paint ourselves into a corner. As other standards appear, we want to remain relevant; we want to create a standard that can be extended without changing what's in its core."

Part of the problem is that SJTAG remains a small group. "A lot of people have expressed interest, but are involved only as observers. We would be able to move forward more quickly if we had more people involved.

"If we can get to the point where we submit a PAR, it might make other pay more attention and take part. Until then, it remains hard to attract their interest."

Heiko Ehrenberg, director of North American operations for Goepel Electronics, is vice chair of the organisation. "I think it's important for SJTAG to have a small core in order to provide the focus for the first standard document. Once that is created, others can provide input to develop extensions.

"Discussions last year highlighted to us that other companies aren't really interested in these activities while we remain a study group. But if we get to the point where we can submit a PAR, then things will be different."

And yet, despite the apparent low level of interest, McIntosh believes many designers are using or thinking about SJTAG-like approaches, but haven't realised they are. "They are effectively using system level techniques to test boards today.

"When you look at an SoC, there are several boundary scan components within the package. When there is one of these SoCs on a board, these more complex devices can be considered as systems in themselves."

While SJTAG is looking for additional members, one useful addition to the development work would be representation from the automotive sector, said McIntosh. "That sector is a big integrator of systems and subsystems. We want end users to be involved; automotive knows the problems that need to be solved," he concluded.

Author
Graham Pitcher

Related Downloads
83498/P33-34.pdf

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