18 May 2001 Solving design management problems Meeting SoC design challenges with a hierarchical synthesis place and route design methodology. By Ashutosh Mauskar. The advent of system on a chip (SoC) design has brought many advantages in design size, speed and functionality. However, it has also placed a far greater burden on the asic flow, which exercises a variety of design tools and methodologies in the effort to deliver quality results with minimal iterations. Physical synthesis tools emerged to solve block level timing convergence from register transfer level (rtl) to GDS II. Their adoption by the mainstream design community is evidence of their ability to accelerate timing closure through the integration of physical and logical design. The next obstacle for ic designers is at the chip level. Because SoC design allows the integration of many functional blocks and cores, problems that were previously addressed at the board level are now evident at the chip level. To achieve final timing closure, designers must incorporate multiple supply voltages, support hierarchical integration of multiple soft blocks, ensure signal and design integrity throughout the hierarchy and solve delay prediction problems. Another challenge of SoC design is to achieve a cost effective level of integration and to establish a clear migration and cost reduction strategy for design derivatives. Author Graham Pitcher Related Downloads 5115\cadence2404.pdf Comment on this article Websites http://www.cadence-europe.com Companies Cadence Design Systems (UK)Ltd This material is protected by MA Business copyright See Terms and Conditions. One-off usage is permitted but bulk copying is not. For multiple copies contact the sales team. What you think about this article: Add your comments Name Email Comments Your comments/feedback may be edited prior to publishing. Not all entries will be published. Please view our Terms and Conditions before leaving a comment.