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Reducing development risk in communications applications

As optical networks, hyperscale data centres and mobile fronthaul/backhaul networks move to higher data rates to support rapidly increasing Internet traffic demands, SerDes reference clock performance is becoming increasingly important.

If reference clock jitter is too high, it results in unacceptably high system bit-error rate (BER), lost traffic or loss of system communication. In addition, 56G PAM4 PHYs, 100G/200G/400G Ethernet, and 100G/400G OTN require a more diverse mix of frequencies, further increasing timing complexity.

The Si54x Ultra Series of oscillator products from Silicon Labs are purpose-built to address the needs of these demanding high-speed communications and data centre applications.

These high-performance oscillators offer any-frequency synthesis, ultra-low jitter of 80 fs RMS and are available in standard, small form factor oscillator footprints. By providing best-in-class jitter margin and frequency flexibility, the Ultra Series is intended to make it easy for hardware designers to de-risk product development.

High-speed communications and data centre timing requirements

*Note: Calculated directly from reference clock or transmitter eye closure specifications budgeting eye closure 50/50 deterministic/rms and 33%/67% clock/transmitter per raw (pre-FEC) BER requirements.

The device can be programmed and customised to meet the target frequency during outgoing test and, by using this approach, the Si54x can be mass customised in order to meet each customer’s unique requirements.

The Si54x Ultra Series supports any frequency from 200kHz to 1.5GHz, enabling a single product family to support both standard and custom frequency applications.

Designed in 55nm CMOS technology, the 4th generation DSPLL leverages a highly digital architecture to deliver improved frequency flexibility and jitter performance.

The input to the DSPLL’s phase detector is converted from analogue to digital, enabling the DSPLL to operate entirely in the digital domain and this all-digital approach has multiple benefits for the design engineer.

First, the Digitally-Controlled Oscillator (DCO) can be precisely steered with a step size as small as < 1 ppb to track out phase delay between the reference and feedback clocks. The DCO gain is small, making the circuit less susceptible to noise than conventional analogue PLLs.

Secondly, the DSPLL supports an innovative phase error cancellation circuit that uses advanced digital signal processing to remove PLL noise due to delay, non-linearity, and temperature effects.

These architectural features ensure consistent device performance across process, voltage and temperature and, as a result, Silicon Labs’ 4th generation DSPLL architecture delivers ultra low jitter across the entire operating range.

Frequency flexibility

When it comes to jitter performance versus operating frequency and temperature the Ultra Series comes with two performance grades. The Si545/6/7 devices provide phase jitter performance of 80fs RMS typical (12kHz–20MHz), whereas the Si540/1/2 devices provide jitter performance of 125 fs RMS typical (12kHz–20MHz).

Given their jitter performance, the Si54x has been designed to maximise jitter margin.

To further simplify device evaluation, Silicon Labs also offers an XO Phase Noise Lookup Utility that can be used to retrieve >1000 measured phase noise plots of oscillators across a wide range of popular frequencies.

Integrated power supply noise regulation

The 4th generation DSPLL also comes with an extensive network of on-chip low drop out regulators to provide power supply noise rejection, ensuring consistently low jitter operation even in noisy system environments.

Another benefit of integrated power supply noise regulation is simplified power supply filtering, PCB design and layout.

Multi-frequency support

In addition to standard single frequency oscillators, dual and quad frequency oscillators leveraging Silicon Labs’ 4th generation DSPLL architecture are available. These devices can replace two or more discrete oscillators with a single IC, helping to minimise both BOM cost and complexity. There are multiple benefits of multi-frequency oscillators:

  • Support multi-protocol SerDes with single device
  • Simplified set up/hold time testing
  • Frequency margining (e.g. 156.25 MHz + 50 ppm, 156.25 MHz, 156.25 MHz -50 ppm)
  • Simplified prototyping. Test new SerDes and ASICs with a variety of reference clocks using a multi frequency oscillator. Transition to a fixed, single frequency oscillator once the final frequency is selected.

Wide range of format options

Silicon Labs’ Ultra Series oscillators have a highly flexible output driver that can be factory customised to support any common signalling format including: LVDS, LVPECL, HCSL, CML, CMOS and dual CMOS.

In addition, the output driver supports a wide supply voltage range. A single Si54x device can support 1.8V-3.3V operation, enabling a si

ngle part number to replace multiple fixed-voltage 1.8V, 2.5V and 3.3V oscillators.

As the demand for oscillators grows so manufacturers are looking to significantly expand their offering to meet the needs of an increasingly complex and demanding market and that includes providing a much broader array of packaging options for design engineers.

To address their demands companies like Silicon Labs are looking to provide a one-stop shop for high-performance oscillators.Ultra Series DSPLL Architecture
Above: The Ultra Series DSPLL Architecture

Author
James Wilson

Related Downloads
167193/P25-26.pdf

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