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Power to their elbow

Power to their elbow

Portfolio updates bring more options to dsp designers.

Portable devices are becoming more sophisticated as designers look to provide users with more features in a smaller package. But they face another challenge; providing the extended battery life that users are coming to expect. Because alongside more features, we're all looking for longer times between charges.

DSPs have, historically, found application in a range of consumer products. While the most obvious of all applications is the mobile 'phone, dsps feature in products ranging from portable media players to headphones. However, the devices are also being specified in what could broadly be termed industrial applications and examples here include medical equipment, as well as biometric devices and seismic detectors.

Just as there are a range of end applications, so too are there a range of power demands. At one end of the scale are high powered designs which are either mains powered or which have a battery operating life measured in hours. At the other end are battery powered devices where the operating life is measured in terms of weeks.

In a move to meet the needs of designers working at both ends of this power spectrum, Texas Instruments has recently updated its dsp portfolio, adding two devices at the low power end and four higher powered parts based on the C647x core, which offers simultaneous floating and fixed point operation.

The two parts aimed at long battery life applications are the TMS320VC5505 and VC5504. According to TI, both parts combine 90nm process technology with low leakage transistor technology to offer what it believes is the industry's lowest standby power consumption for such devices. Alongside this, the dsps maximise energy efficiency and extend battery life in portable devices.

One of the benefits claimed for the parts is their feature and cost flexibility, allowing them to be designed into a range of applications. Potential applications include portable voice/audio products, portable medical devices, smart sensors and software defined radios.

Improved power management – combined with multiple additional power down states, dynamic frequency, voltage scaling, clock gating, the freedom to turn on and off individual peripherals and other power saving architectural features – allows for maximum battery life.

The power consumption of both devices can be as low as 18mW at 60MHz, which also allows designers to add more features without decreasing battery life.

The C5505, which runs at up to 100MHz, is a fixed point device based on the TMS320C55 cpu core. The cpu supports one program bus, one 32bit data read bus and two 16bit data read buses. There are also two 16bit data write buses and additional buses supporting peripheral and DMA activity. This combination allows the device to perform up to four 16bit data reads and two 16bit data writes in one cycle.

There are two MAC units, each capable of performing a 17 x 17 multiplication and a 32bit add per cycle. A central 40bit alu is supported by a further 16bit alu, both under instruction set control, providing the ability to optimise parallel activity and power consumption.

General purpose I/O functions, along with the 10bit SAR a/d converter, provide sufficient pins for status, interrupts and bit I/O for lcds, keyboards, and media interfaces.

The peripheral set includes an external memory interface that provides access to a range of asynchronous memories. Additional peripherals include a USB2.0 device mode only port and a real time clock. Also featured are three general purpose timers, one of which is configurable as a watchdog timer, and an analogue phase locked loop.

The C5505 offers up to 320kbyte of on chip ram, 64kbyte of which is dual access, while the C5504 has 256kbyte of ram and 64kbyte of dual access memory. Both parts feature 128kbyte of rom.
Two core voltage options can be specified. The 1V core will run at up to 60MHz, while the 1.3V variant can run at up to 100MHz.

More power
Catering for the higher power end of the spectrum, TI has recently launched three dsps based on the C674x core.
Kanika Carver is C674x and OMAP-L13x processor marketing manager for Texas Instruments. "While the 5504/5 measure power efficiency in terms of µV and battery life in weeks, the C6742/6/8 are aimed at designs where the battery life is a matter of hours." While the three parts are suited to audio style applications, Carver said 50% of the target applications for the new processors fell into the industrial category. "Some of the things we're seeing include test and measurement, industrial monitoring and programmable automation control."

The TMS320C674x is TI's first core to combine fixed and floating point capability. The company says it's not a dual core implementation; rather, it is a superset of the C64x+ instruction set and the C67x+ instruction set. On every instruction cycle, the C674x can either execute the C64x+ fixed point instructions or C67x+ floating point instructions or both.

The C6742 is a 200MHz device with 128k of on chip memory. Carver said the peripheral set was targeted at audio style applications. The C6746 is a 300MHz part with 320k of memory, along with an Ethernet MAC and USB 2.0. "It has a universal parallel port," she continued, "which allows the device to be interfaced to high speed a/d converters at data rates of up to 150Mbyte/s." The UPP is programmable to accept data widths ranging from 8 to 16bit.

Completing the line up is the C6748, another 300MHz device with similar features to the C6746, but which adds a SATA interface. "It's the first time a device of this class has featured a SATA port," Carver noted. "Normally, this is found on something like a PowerPC."

All three parts feature dynamic voltage and frequency scaling. "This allows users to optimise their design for power and performance," she concluded, "and this hasn't been offered on any TI processor before."

SHARC powers StudioLive system
PreSonus has used Analog Devices' 32bit floating point SHARC 21369 processor, its StudioLive 16.4.2 digital audio mixer and multichannel recording system to help to provide high performance and sound quality in a compact, affordable system.

PreSonus needed a processor that could support intensive mixing and dynamic effects processing. The original StudioLive design incorporated an fpga as the primary processor, but PreSonus' engineers determined this would have unacceptably high latency, while making the implementation of complex audio effects difficult.

With the floating point SHARC architecture, PreSonus gained high computational power, as well as a robust instruction set that allowed greater flexibility for programming and customising audio algorithms. PreSonus selected SHARC on the strength of its 400MHz/2.4GLOPS floating point performance, as well as its on chip memory.

SHARC's flexibility helps OEMs to differentiate their products. For example, PreSonus developed a task scheduling kernel that uses SHARC's direct memory access to mix and process live audio streams with low latency. This kernel helps manage the dynamic allocation of resources and memory and minimises overhead via an eight frame sample cycle.

Author
Graham Pitcher

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