23 June 2005
Power point
New eda tools for power analysis should help to optimise SoCs for low power operation and improve design efficiency. By Louise Joselyn.
Demand for battery powered devices with higher functionality, higher performance and lower power consumption means SoC designers are struggling to resolve conflicting constraints.
A common strategy for reducing power is to reduce supply voltage. But this can lead to lower noise margins and a potential increase in sensitivity to such problems as crosstalk. Meanwhile, higher performance means higher clock rates, which not only increase dynamic power, but also parasitic effects. Further, greater density and smaller process geometries bring more leakage current, which means continued power dissipation even when a circuit is idle. But, for a typical cmos SoC, dynamic power dissipation is the prime consumer of power.
Author
Louise Joselyn
Supporting Information
Downloads
5570\power-point.pdf
Websites
http://www.cadence.com
http://www.magma-da.com
http://www.silicondesignchain.org
http://www.synopsys.com
Companies
Cadence Design Systems Ltd
Magma Design Automation
Synopsys Northern Europe Ltd
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