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Outlook 2013: Leading the way

One of the trends during the 21st Century has been the integration of SoC like components into an FPGA fabric.

Today, all major FPGA vendors offer devices with built in math blocks, high speed serial interfaces and microprocessor cores. But integration is not the only way to meet customer requirements and, looking ahead, 2013 is going to be an exciting year for FPGAs, because technological developments will make FPGAs the leading way to implement systems that require:

• security
• low power
• reliability
• integration

These developments will create a new way for designers of medical, industrial and military systems to develop differentiated products.

Need for security

All FPGA configurations need to be protected from being cloned, reverse engineered or tampered with. Design security protects the FPGA from design theft and/or alteration.

Many FPGAs have some design security included in their feature set, but using it can be difficult. The greatest advances in device security will come from making base level security easy to use and adopt. The ideal situation is to provide security that works inherently, without the need to do anything to implement it.

One of the issues with SRAM based FPGAs is the need to configure the device every time it is turned on. Normally, the configuration is loaded from an external memory device, exposing the design bit stream over the link between the two devices.

However, by storing the configuration information in non volatile memory on chip, the bit stream is never exposed and that makes it impossible to capture the information. This inherent security stops your design from being copied and any proprietary IP from being stolen and redistributed to a competitor. It also prevents the design being tampered with for malicious effect.

Current generations of FPGAs only provide design security. New security features will also address data security, the protection of the application data that the FPGA is processing. Examples of data security features are:

• hardware protection from differential power analysis attacks
• non deterministic random bit (number) generator
• hardware firewalls to protect the integrated ARM Cortex-M3 microcontroller core

Need for low power

Low power consumption is critical in many systems but while microprocessors and microcontrollers have included power saving modes for years, these low power modes have not been available in FPGAs until now.

Many systems operate reactively or periodically and, for those systems, the opportunity to reduce power by 95% (or more) is possible. A reactive operation is when the system is in a standby state waiting for an event to trigger some processing activity. Once the processing has been completed, the system returns to its standby state. Examples of systems that use reactive power schemes are patient health monitor alarms and movement sensors in security alarms. With periodic operation, processing activity takes place on a recurring basis. While the device is not processing, it can be placed into a standby mode. In both reactive and periodic cases, the standby mode reduces power by placing the FPGA in a very low power mode between the bursts of activity. Examples of periodic systems are standard wireless protocols and heart rate monitors.

All SRAM based FPGAs consume large amounts of static power just to remain operational. The only option for a low power mode is to turn the whole device off, which means the FPGA's state needs to be saved before turning it off. On exit from the 'low power' state, the FPGA must first be reconfigured; only when restored to its previous state can the operation continue. These power up constraints make it impossible to implement reactive or periodic power saving schemes in SRAM based FPGAs.

Low power modes have been implemented in non volatile memory based FPGAs for the first time. The Flash*Freeze low power modes available in Microsemi devices can be entered into and exited from without affecting register and SRAM states or the FPGA's I/Os. The microprocessor subsystem, along with its peripherals and I/Os, can remain operational throughout this time if desired. Flash*Freeze mode can be entered into and exited from in 100µs.

Military systems are required to meet system weight and power (SWaP) targets in order to meet budgets and extend operational life of a product. SWaP targets are intended to extend mission life and reduce form factor for better mobility and logistics.

Need for reliability

Military and industrial systems are coming under scrutiny for their reliability. Military systems must operate flawlessly after (often) prolonged periods of storage. Meanwhile, industrial systems are increasingly required to meet safety standards before they can be delivered to end equipment users and the need for reliability in medical systems has always been a focus area.

Reliability issues in FPGAs are mostly caused by single event upsets (SEU) changing the contents of the configuration SRAM. This SRAM controls the routing and logic configuration of the device and any change will cause an error in the design. This is an issue that is largely ignored or even hidden by vendors of SRAM based FPGAs.

SEU effects are caused by Alpha particles in the device's packaging or by neutrons present in the atmosphere; both contain sufficient charge to change the content of one or more bits in an SRAM.

Flash memory based FPGAs are immune to the effects of an SEU, eliminating the possibility of design corruption and removing the most common failure mode from a system. It also eliminates the need for SEU mitigation found in some SRAM based FPGAs. This approach takes time to detect a fault and if possible correct it, during which the damage can already be done.

Reliable operation should also be safe operation. Many industrial and medical systems need to operate in a safety critical fashion in order to prevent harm to users. A fault arising from an SEU could, in an SRAM based FPGA, cause industrial or medical machinery to fail and cause injury. Using a flash memory based FPGA will remove this risk.

As they become used in volume designs, FPGAs need increased integration to reduce cost and power consumption. FPGAs often integrate functionality such as:

• embedded processor cores
• high speed memory interfaces
• multi gigabit serial I/Os

Need for integration

Integration of an embedded processor core removes the need for a soft processor core to be created in the FPGA fabric and the speed and size penalties of this approach. The same is true of tightly coupling peripherals and subsystems, such as memory controllers and communication protocol interfaces.

A non volatile FPGA does not need a separate memory to hold the device configuration. Integrating FPGAs with other components, such as microprocessors, memory devices and DDR memory interfaces, reduces the component count on a board. Overall, this reduces total system cost, reduces overall power consumption and improves reliability.

The major advancements in FPGA technology for 2013 will be in the fields of:

• security
• low power
• reliability
• integration

These developments will create a new solution for the designers of medical, industrial and military systems and their need for differentiated products. Designers of highly reliable, secure and low power embedded systems will no longer just have a FPGA or a microcontroller (or potentially both), to consider; they will now have access to a system on chip FPGA that inherently solves the four major needs of system design.

Microsemi offers a comprehensive portfolio of semiconductor solutions for: aerospace, defence and security; enterprise and communications; and industrial and alternative energy markets. Products include high performance, high reliability analogue and RF devices, mixed signal and RF integrated circuits, customisable SoCs, FPGAs, and complete subsystems. Headquartered in Aliso Viejo, California, Microsemi has approximately 3000 employees globally.

Paul Ekas, Vice President of Marketing, SoC Product Group, Microsemi

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