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Only a mother can tell them apart

Has moving from a programmable to a hardwired gate array ever been easier? By Philip Ling.

You may be forgiven for thinking that the gate array conversion route is only open to a few, high volume users. The truth is that the barriers to adopting this low cost asic solution are tumbling, which could see a revival in the proven technology.

The term 'gate array' is essentially the best way of describing what it is – a two dimensional array of uncommitted, but adjacent, n and p type transistors. Arranged in rows and columns, multiples of the two complementary metal oxide silicon (cmos) transistors together make gates. Any logical block can be made from cmos gates connected in the right way. The simplest is the NOT gate; essentially two complementary transistors, or one cmos gate.

By fabricating these gate arrays on a wafer as 'blanks' or 'masters', costs can be kept down, with customisation at the routing stage. Performance needn't suffer either, an example is Texas Instruments, which has, in the past, used gate array technology to fabricate its own high performance dsps.

So why has the technology taken a back seat? Well, minimum order quantities require a lot of confidence in demand from the customer, while the initial outlay for mask sets (for routing) represent a significant cost, the non recurring engineering (nre) cost. Stacked against the falling cost of programmable gate arrays, these financial commitments could prove too high for the savings made per unit shipped.

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Author
Graham Pitcher

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