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Only a matter of time

Processors running at more than 1GHz are a reality, but what keeps them ticking? By Philip Ling.

The double edged sword of continued feature size reductions and increased silicon die area brings with it an economy of scale but also some challenging problems for asic designers. Even for those engineers not designing at the transistor level, for instance when using an fpga, achieving timing closure across large designs all too often involves compromise.

One of the biggest challenges – and one which unites almost all designs based on dense digital logic – is how to clock these complex, multiple circuits when they are distributed around large pieces of silicon. And, once that is achieved, there is invariably a request to make it go even faster.

The performance of a processor can be evaluated in many ways, but it is generally accepted today that the faster the clock, the higher the performance. Whilst this may well soon be accompanied by power density as a measure of useable performance, at the moment, the majority of design effort goes into making transistors not only smaller, but also faster.

If faster switching speed is the aim, then driving the switched signals across large die areas and with multiple loads is the primary design constraint, and nowhere is this more apparent than in the clocking structure.

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Author
Graham Pitcher

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