14 February 2012

Offloading tasks from the microcontroller can improve power efficiency

The single biggest concern among microcontroller users used to be system cost, but energy consumption has steadily become a bigger issue.

Process migration and improved circuit design have resulted in major power savings over the years. However, this exposed leakage current as a major source of energy loss, particularly in systems that need to be powered by a single battery charge over their entire expected lifetime.

The response from microcontroller makers was to reduce the current consumed by the device when it has nothing to do. The processor core and many of the peripherals can be put to sleep and the supply rails disabled, leaving the device running the bare minimum of support functions on circuits tuned for leakage.

Jason Tollefson, senior product marketing manager at Microchip Technology, says: "When we introduced our XLP family, we drove sleep current to such low levels that it's hard to get much more out of that. The next place for significant savings is to do more in sleep that would have been considered active mode operations in the past, as well as reducing active current altogether.

"We are finding there are two areas that consume current: flash accesses and ram. Anything we can do to reduce the number of hits on those two elements will give us an advantage."

Gordon Cooper, product marketing manager at NXP, says: "The longer the cpu remains sleeping, the greater the potential power savings."



Intelligent peripherals can help by writing data into memory buffers ready for processing by the processor when it next wakes from sleep. However, this automated collection of data does not help the cpu in systems where latency is crucial or where long periods of time pass by before any data arrives that is genuinely of interest. Without help, the cpu still has to wake up to process each captured sample individually to determine whether a critical threshold has been exceeded or whether incoming data was relevant.

Rasmus Larsen, support and training manager at Energy Micro, says: "When interfacing with a lot of sensors, we found that processors have to be awake quite a lot."

Capacitive touchscreens present a particularly difficult challenge for low power microcontrollers. Typically, the sensor uses an excitation circuit based on an RC oscillator to generate a periodic voltage wave. As the users' finger approaches the display, the capacitance changes and reduces the oscillation frequency. An mcu will normally sense this change by comparing the output of a pulse counter with a timer that is reset at regular intervals. The processor could sleep for intervals and wake up to check the frequency of the incoming signal. But the longer the gap between these checks, the less responsive the system will seem.

By moving the comparison logic to hardware, the processor core need only be woken when the sensor indicates that the something has touched the display.

"Without this hardware, the processor would have to wake up regularly only to find there is nothing happening. And you have to spend a lot of energy in waking up the CPU," says Larsen.



Other peripherals benefit from the same approach. For example, if address checking logic is built into their serial ports, there is no need for all the processors on a multidrop bus to wake up and check whether an incoming packet is for them, just the microcontroller that has been addressed directly.

Some suppliers, such as Energy Micro and NXP, have opted to develop intelligent peripheral controllers, based on configurable state machines, to control peripherals while the processor sleeps. Larsen says the state machine approach adopted for the Lesense controller in the EFM32 Gecko mcu family makes it possible to control the actions of a number of different I/O blocks.

The NXP LPC4300, meanwhile, has what the company calls a state configurable timer; a hardware block that switches between states based on I/O and events created by the built in timers. Cooper explains: "For example, if the application needs to create a pulse from a change on a pin, the state configurable timer can create this pulse autonomously without any help from the core: it remains asleep.

"We chose a state machine approach because state machines are very familiar to engineers. This is a much less complex approach then creating a new programmable 'language'."

Atmel, with its SleepWalking architecture for the AVR family, and Microchip have opted to build intelligence directly into the peripherals themselves.

Tollefson says: "We will implement hardware assists, but do it within specific scenarios. A touch sensor that runs in sleep is one we wanted to enable specifically. Encryption is something we would like to do in hardware because it's much more energy efficient than doing it in software. And we are also thinking of doing more automation in wireless applications to eliminate accesses to flash and ram as much as possible. I don't see it being a wholesale generic approach."

Cirrus Logic has adopted a different approach to I/O offloading, concentrating more on development time than on power consumption. The company has combined a digital signal processor running code in mask rom with sigma-delta a/d converters to build a smart front end for microcontrollers in energy meters.

Ed Sarrat, Cirrus' global product marketing manager, says the idea behind the front end is to reduce the development burden by providing energy related measurements, such as power factor, rather than pulses from a sensor.

"There are utility meter engineers who could absolutely write the code, but we see a trend towards home energy management: putting these measurements into appliances directly. That is where they really get the benefit from a preprogrammed device," says Sarrat.

Secondary low power processors are appearing in high integration microcontrollers such as the LPC4300, which combines an ARM Cortex-M4 with a lower power M0. The same approach is becoming a key part of chipmakers' strategies for smartphones, as seen with the launch of ARM's Big.Little system and nVidia's Tegra3 embedded processor, which includes a slower but lower power, Cortex-A9 that is used instead of the regular A9s when the workload is light.

The increased use of multiple voltage domains on microcontrollers increases the options for using low power logic.

Tollefson claims: "You would be amazed at the technology we are developing to try to squeeze nanoamps out of our circuits. With our multiple voltage islands, we are doing things to manipulate the leakage current without having to turn them off completely."

Similar concepts are being readied for use in higher end processors. For example, Intel engineers described at last year's Design Automation Conference encryption cores for intended for future implementations of the x86 architecture that use subthreshold logic. Operating at less than the conventional threshold voltage, these circuits are very slow, but offer much lower active power consumption than conventional circuitry. The technique is already used in devices such as the Sensium smart plaster developed by Toumaz Technology.

Without dramatic reductions in memory and bus power consumption, the trend to take work away from the core processor is set to continue.

Author
Chris Edwards

Supporting Information

Downloads
40298\P24-25.pdf

Companies
ARM Ltd
Atmel Corporation
Microchip Technology Inc
Nvidia Technology UK Ltd
NXP Semiconductors

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