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No need to take a risc

Perfect working partnership pushes power efficient processor to market.

When CML Microsystems purchased fabless semiconductor company Hyperstone in July 2003, it opened the floodgates for a range of microcontroller products based on unified risc/dsp architecture.
Today, CML Microcircuits UK and Hyperstone, both part of the CML Microsystems Group, have established what seems to be the perfect working partnership. Founded in 1990, Hyperstone's research and development centres concentrated on establishing innovative designs of risc/dsp process architecture, but as CML's marketing manager Malcolm Lyman noted, it did not have the resources to push products to market on a grand scale. "The products effectively outgrew the company," he explained, "but CML has the resources to get them out there."
With CML's backing, the innovative microcontrollers are being relaunched to a much larger customer base.
According to Lyman, Hyperstone's core architecture provides both a fast risc processor for data and control functions, together with a powerful dsp unit for efficient algorithm execution. "Hyperstone's designs require less silicon, are more power efficient and require lower software complexity when compared to conventional dual core designs." Since CML acquired the organisation, it has shipped more than 55million microcontrollers into fast growing markets, primarily flash memory cards.
The current focus is the E2 microcontroller, which Lyman describes as 'filling the gap' for those who want to take an easy step up from 8bit into 32bit. The E2 has been chiefly designed for use in industrial sensing and control applications, but is also suitable for cost sensitive metering and scanning applications. Because the 32bit market is the fastest growing sector of the microcontroller market, to actively contend in such a competitive market is a testament to the faith that CML has in Hyperstone's designers.
"The microcontroller evolved from Hyperstone's earlier E1 risc/dsp core, which first appeared in 1990," said Lyman. "However, the E2 has additional peripherals, such as an added programmable serial communication engine to make it more palatable for customers. It uses the same feature set, but is enhanced by an a/d converter and 32kbyte on chip ram for instruction storage, complemented by an external memory and peripheral interface controller. This allows for much easier integration into customers' designs, reducing the number of external components and optimising the board layout.
The E2 is ROHS compliant and, at 640MOPS/160MHz peak, it offers what Lyman describes as 'industry leading performance'. Again, CML's corporate backing has allowed the Hyperstone microcontroller to be backed up by global technical design support and a development kit, which eases migration and helps speed up time to market. The development kit includes a populated board, software tools, C/C++ compiler, linker, assembler, source level debugger with profiler, runtime kernel and dsp library.
Lyman added: "Hyperstone's minimum transistor count results in an extremely low power consumption, depending on process technology and maximum frequency. For example, at 200MHz, the processor will consume about 50mW." An automatic power down reduces consumption even further, depending on the application. Due to the on chip bus interface, total power consumption depends on the external load connected to the chip, but the low power consumption makes very small packages possible. This is of particular use for mobile portable applications or in temperature sensitive environments.
As Lyman explained, the E2 microcontroller evolved from the earlier E1 core, using as its basis the combination of a risc processor, dsp set and on chip microcontroller functions. "Hyperstone's risc technology is based on a load store architecture," noted Lyman. "It is register orientated and built around a 32bit wide register stack that holds general purpose local registers and 26 global registers."
The E1's load and store instructions are pipelined to a depth of two stages at the memory bus. The dsp unit also operates on the register set of the architecture in parallel to the load/store unit. It executes a dedicated dsp instruction set and, like the other instructions, the dsp instructions strictly follow risc principles. Lyman added: "During the latency cycles of dsp instructions, the load/store unit can execute other instructions. Thus, a much higher degree of flexibility is achieved compared to conventional dsp implementations. Additionally, up to three operations per clock cycle can be executed, so a peak performance of up to 300MOPS can be achieved at 100MHz."
Hyperstone's risc/dsp architecture has a set of 96 32bit registers, of which 64 are local registers and the others are global registers. The register stack is organised as a circular buffer and uses the concept of overlapping stack frames. The processors use variable length instructions with 16, 32, and 48bit instructions.
Lyman observed: "Very useful are the integrated timers, the interrupt handler and the comprehensive bus interface for glueless connection of any kind of memory and periphery. An automatic power down mechanism further reduces the low power consumption which is one result of the compact design."
The variable length 16, 32, or 48bit instructions, automatically prefetched by the E1, can support constants and native addresses of 16 and 32bits. The 4Gbyte address memory space is divided into seven blocks, internal functions, on chip sram and five external memory areas.
Lyman noted: "Each external block can be user configured in software for bus width, timing and memory type. The memory interface supports glueless connection of dram, sram, eprom, flash or other memory mapped devices. The separate I/O address space also allows each I/O device to have its own timing."
Lyman is clearly pleased with how well the companies complement one another. "Hyperstone allows us to open up to totally different markets, such as flash memory controller applications, industrial environments and replacements for hard drives."
With the design expertise to hand, later this year CML will be pushing another system based on the E2 core, but with additions such as Ethernet controllers. Lyman explained: "The Hynet communication controller is an existing product, but until now, Hyperstone did not have the capabilities to push it to a larger market."
According to Lyman, the system is built on a proven technology platform and can be used in a range of applications. "Hynet is an easy to program risc/dsp architecture with all the features required for network enabling and communications within the embedded applications world. An integrated SoC, it features a performance of 200MIPS and up to 800MOPS, along with versatile interface options and power saving features."
There are a wide range of potential applications including security, IP cameras, VOIP, network enabling and industrial automation.
The strength of CML and Hyperstone's union is the fact that sales distribution and global support can now be made available to both new and existing customers. The acquisition has allowed the latter's products to be taken forward and to increase both companies' global user base and, crucially, the overall market position.

Chris Shaw

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