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New transistor design tackles threshold voltage variability issues

New transistor design tackles threshold voltage variability issues
New transistor design tackles threshold voltage variability issues

As cmos transistors continue to get smaller and smaller, it becomes increasingly difficult to make them behave in a similar fashion. With more and more transistors being packed into smaller areas of silicon, the consequence is that more devices are likely to fail to meet design requirements.

The reason at the heart of this is variability. In order to make silicon behave in a particular fashion, it's doped with small quantities of other elements.

At larger process dimensions, there were enough dopant atoms around to ensure the 'right number' were in any given volume of silicon. But as the semiconductor industry contemplates life beyond the 20nm node, manufacturers can't be sure there will be an even distribution of dopant atoms throughout the base silicon. So, while some transistors will have the right number of dopant atoms, others will have too few and will not operate correctly.

One solution takes advantage of the fact that, at 20nm, transistors are, effectively, free. By including more than are needed, the chances are there will be enough 'good' ones to make the circuit work – a variation on redundancy. But another solution is to address how the transistor works; and that's what SuVolta is addressing as part of its PowerShrink platform.

There is a general agreement in the semiconductor world that transistor design holds the key to the future. Paul Otellini, Intel's president and ceo, has said 'transistors are going to be a defining point of differentiation'. "Better graphics performance in a battery constrained environment is going to be a function of the transistor," he said.

Jeff Lewis, SuVolta's senior vp for marketing and business development, noted: "I agree with the concept, but not with the implementation. We are both trying to solve the same problems, but in a different way."

SuVolta described its approach – which it calls the Deeply Depleted Channel (DDC) transistor – at last year's International Electron Device Meeting.

Variability can express itself in a number of ways, but a major effect relates to power consumption. Users continue to demand better power efficiency from mobile devices. This has traditionally been provided by moving to smaller process geometries and lower voltages.

"Power is a primary issue," Lewis noted, "and it's an exponential function of voltage." Because of the variability issue, it's getting a lot harder to reduce voltage.

As Lewis accepted, a number of different approaches to transistor design are being pursued. But he believes these are focused more at solving problems inherent to the pc market than they are to solving issues for SoC designers. "FinFETs are good solutions," he said, "but they are targeted at desktop microprocessors and are not necessarily a solution for mobile SoCs." Other avenues of research he highlighted included Imec's fully depleted silicon on insulator and Intel's bulk planar transistors.





But the underlying problem is variability and SuVolta's approach is intended to reduce this. "When you tighten the distribution," Lewis continued, "you solve two problems; you get rid of leaky transistors and you get rid of slow transistors." In fig 3, the left hand side shows the effect of tightening distribution on leaky transistors. "Tightening the distribution on the right hand side gets rid of slow transistors," Lewis pointed out.

Despite his belief that broader market solutions will win in the end, Lewis concedes that Intel's FinFET approach will lead the market in the near term. "Intel will get the trigate/FinFet working, but this technology will be difficult for foundries to implement and optimise. Intel will be able to debug the technology because it will produce about 2million wafers using the trigate flow over the next two years."





But in the longer term, Lewis believes low power SoCs will drive semiconductor developments, not cpus. "A radical shift will be needed in order to allow the industry to support the manufacture of $10 chips, not $200 microprocessors. With microprocessors, it's all about performance. SoCs, on the other hand, have to blend power, performance and cost."

So how does SuVolta's solution achieve its aim? SuVolta's DDC approach has three layers. The first layer is the channel, from which as many dopant atoms are removed as possible. Lewis said: "The key is an undoped or lightly doped stack. We have modified what lies underneath, but the gates and other areas remain the same. By effectively removing dopants, we get better Vt matching and we do this in a way which can be integrated into existing fabrication methods.

"There is tight control of the depletion depth," Lewis continued, "and an improvement in Vt matching."

He said the process has already been implemented into a number of fabs. "All have been able to bring the technology up without modifying their equipment or materials. This makes it compatible with an SoC design flow, where multiple Vts can be supported."

The second level is the Vt setting offset region. "Here, we can change the doping to vary threshold voltage levels without degrading channel mobility," Lewis noted.

Finally, the third level is the screening region. "This is a highly doped region," Lewis continued, "which constrains depletion and serves as a barrier if biasing is needed. It's an effective way of controlling Vt dynamically and performing power gating."

According to SuVolta, the approach brings a number of benefits. Because there is lower threshold voltage variation, leakage is lower and so is power consumption. Meanwhile, higher channel mobility brings better performance, while a reduction in drain induced barrier lowering supports increased density as processes scale to smaller geometries. "And there's a doubling in the body coefficient," Lewis claimed, "bringing increased control over Vt and reduced power consumption."

SuVolta now has its sights on the 28 and 20nm nodes. Lewis said: "We have the transistor working at 28nm. Good short channel effects show the approach is scalable beyond that."

Why has this approach not been introduced before? "Power wasn't as much of a driver as it is today," Lewis admitted. "Before, people were more interested in driving density. There are also better, more accurate tools available today," he added.

* Meanwhile, in a demonstration, Fujitsu has integrated DDC technology into its low power 65nm process technology and shown that a 576kbit sram block can operate from a 0.425V supply by reducing cmos transistor threshold voltage variation by half.

Lewis said: "Fujitsu measured 222m transistors and not only found a fivefold reduction in leakage, but also a much tighter distribution. SRAM is the first thing to stop running when the voltage decreases and this implies the DDC approach could enable a range of cmos based circuits to run from a supply of around 0.4V.

"Fujitsu has implemented the technology 'across the board' at 65nm and production is planned for the second half of 2012," he concluded.

Author
Graham Pitcher

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