09 March 2009
Mixing it up
Addressing the mixed signal system on chip design challenge.
As cmos process technologies continue to evolve, so too do the opportunities for developing integrated SoCs that satisfy more of the overall system requirement. As no system is ever purely digital, there is a corresponding and growing requirement for linking core processing functionality with the outside world via analogue and mixed signal IP blocks. However, there are a number of factors that need to be carefully considered if the inherent – and potentially costly – risks of integrating such blocks into the SoC design are to be avoided.
At the heart of any SoC development will be the choice of process technology. Today’s mainstream cmos process offerings cover 130nm, 90nm and 65nm, although more mature technologies between 0.18µm and 0.8µm remain in production.
The key is to carefully match the process to the specific requirements of the target application. The performance, size and power demands of next generation consumer and mass market applications, such as mobile phones and portable multimedia players, may require the high density and low power consumption provided by a 65nm technology. However, an SoC processing just a few lines of 2.5Gbit/s PCI Express signal functionality may be better suited to a less costly 90nm process.
At the heart of any SoC solution will be a digital processor; another important design consideration. For instance, licensing ARM technology and the ability to provide synthesisable ARM cores is becoming increasingly important to companies that offer asic development and foundry services.
It must also be recognised that getting the best performance from the digital processor core is tightly coupled with the availability of suitable embedded memories. Each of Toshiba’s asic technologies offers a choice of embedded sram, register file and rom architectures. Each architecture is optimised for a variety of specific applications, such as high density, high speed, low power, efficiency for small blocks, efficiency for large blocks, single port, dual and multiport access. All can be compiled in a wide range of words and bits.
The requirement to link core digital processing functionality with the real world means that an important consideration is how best to implement the d/a, a/d, serial to parallel and parallel to serial elements. Rather than designing these elements from the ‘ground up’, the sourcing of silicon proven, robust analogue and mixed signal and analogue intellectual property (IP) has become a critical factor.
It is this requirement for readily available IP that has led to the emergence of an industry based around third party IP vendors, foundry manufacturing and eda companies. However, a growing number of ODMs, OEMs and fabless chip companies are beginning to realise there are inherent risks associated with this model: in particular, sourcing IP that has yet to be proven in the target silicon.
It is essential, therefore, that SoC designers assess how simple it will actually be to integrate the IP into the target design and how likely it is that everything will work the first time around. Tight time to market windows and budget pressures mean the objective has to be to minimise the technical and commercial risks associated with respins. Among the factors to consider is the potential for the ‘blurring’ of the boundaries of responsibility – which supplier (IP provider or foundry) will take responsibility for a problem and provide the support needed to resolve issues.
However, IP from independent vendors can prove highly suitable for the rapid integration of standard connectivity blocks into an SoC – at least up to functional sampling. The limitations, however, start to become apparent when it comes to addressing tough specifications and tight process/production windows. IP for a/d and d/a converters and for PLLs, for example, requires many parameters to be optimised, while the multiple standards and wide range of potential configurations of a serdes implementation means project issues dominate and customisation is almost always needed.
Recognising these limitations means those looking to create advanced SoCs are actively seeking alternative supplier models that can better meet their design and development requirements. One such model is the integrated device manufacturer, IDM. In the IDM model, the supplier provides total SoC competence – from IP development and support to semiconductor fabrication – allowing customers to deal with one organisation from design to manufacture. And an important element of a successful IDM model is the strategy taken towards the availability of mixed signal IP. Toshiba’s IP strategy is specifically targeted at minimising risk for the customer.
Author
Rainer Kaese and Eugen Pfumfel
Supporting Information
Downloads
17392\P25-26.pdf
Websites
http://www.toshiba-europe.com/
Companies
Toshiba Electronics Europe GmbH - UK Branch
This material is protected by Findlay Media copyright
See Terms
and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the
sales team.