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Low power verification methodology

Low power verification methodology

The world of electronic design automation (EDA) seems to continue to evolve in a predictable fashion. But, asks Krishna Balachandran, is this a case of natural evolution?

New design challenges call for new techniques, which break the existing design flows. There is an immediate impact on verification, which needs to retool to detect new classes of bugs. New tools and methodologies initially start as semi-automated aids for design automation. Eventually, the problems are well understood and a documented methodology emerges to replace the existing methodology for both design and verification until the technology changes, and it is déjà-vu all over again.

The EDA industry is in no way immune to the changes imposed by low power. If anything, power managed designs have had a far greater and more rapid impact than previous technological seismic shifts. Verification tools have had to deal with a host of new design elements and language deficiencies to model voltage values.

New power intent languages have surfaced and vied for standardisation. Low power verification tools have competed on the grounds of accuracy and with the promise of detecting bugs before they manifest themselves in silicon. In the midst of all these sea changes, it is only natural that verification methodology has to be re-defined to handle low power.

Importance of a verification methodology for low power
Commercially available verification tools are designed for a broad range of customers. Semiconductor designers do not all follow the same design styles – if they did, they would not have a competitive advantage. Therefore, different design methodologies exist in the industry leading to the need to customise the verification environment to match the chosen design style.

Large companies working on multiple low power projects in parallel also have the desire to standardise the way they verify their designs. Without a structured and methodical process, verification teams within these companies use their own self-grown scripts and programs that become untenable to maintain.

There is a lack of shared understanding within the teams on how to uncover low power bugs without a documented, repeatable verification process. Even worse, the lessons learned from one team engaged in a low power tape-out can't be leveraged across other teams.

A verification methodology for low power solves all these problems with one stroke. It can significantly improve the timely delivery of projects, the ability to detect bugs in the factory rather than in the field, and ultimately, the company's ability to bring to market high quality products in a profitable manner. Tools alone can't do this because they do not enforce a methodology.

Bug classification
Designs targeted for low power are fundamentally different from those that are not. Low power designs incorporate circuits to manage power, which are not described in the design's original specification. Traditional verification tools don't understand the presence or absence of these circuits and their impact on design behaviour.

Correct insertion and connection of the power management circuits are essential to proper operation of the entire device. The device elements used to manage power can function incorrectly or be improperly inserted or connected. Low power designs typically turn on and off power domains (regions of the chip), and an improperly designed or connected power management device can result in the functional failure of the entire device.

There are a host of new bugs that arise with the presence of these added design elements. A thorough classification of the new bug types and their causes is strongly needed by an industry plagued by the task of getting low power designs to work out-of-the box. Consequently, any low power verification methodology must first attempt to classify all low power bugs and suggest rules and guidelines to verify as well as avoid them.

Verification advice
Low power designs have changed the verification paradigm forever. In the non low power world, the entire design operated at a single voltage and all parts of the chip stayed on and operated at the specified voltage. Low power designs segment the chip into different regions that can be independently turned on or off. Multiple voltages are also increasingly used to control power even more aggressively. These changes imply a whole new way of looking at the verification task.

The first step is to capture the power specification of a chip. Bugs in the power specification will almost always lead to functional issues going undetected until they are seen in silicon. Any well conceived verification methodology must first be able to critique the power intent. Verification now must comprehend the power modes of a design. Test benches must be enhanced to exercise the power modes. Incomplete verification of the power modes, power states, transitions and sequences may lead to expensive field failures. Verification plans, written before the impact of low power design was considered, must be completely rehashed. Industry best practices for low power design verification are likely to replace existing verification methodologies.

There is now a burning need for a comprehensive list of dos and don'ts for low power verification. This is best addressed by a low power verification methodology that incorporates lessons learned from real life designs.

Structured and repeatable verification infrastructure
Companies engaged in multiple low power designs strive to reuse successful best practices across design teams. Without a repeatable and structured methodology, this is an ad-hoc process that is not scalable.

Many low power designs use a combination of software and firmware to control power. A low power verification methodology needs to address not only the hardware, but also the verification of the firmware.

Finally, a low power verification methodology must also provide for the setup for an easily replicable verification environment. Base classes that can capture the necessary building blocks of a low power verification test bench can quickly assist with replicating the verification environment required for the successful detection of low power bugs; therefore they are an integral part of a well conceived verification methodology.

Conclusion
Designers of low power will unanimously agree that verification is the single most limiting factor in getting a working design out on time. With the cost of verification rising astronomically, it is uneconomical to continue using ad hoc methods. Low power verification needs a codified, documented and repeatable methodology that can be readily deployed.

A low power verification methodology based on experience garnered from real designs that can replicate silicon success is a natural evolution for the EDA and semiconductor industries.

Author
Krishna Balachandran, director of product marketing, low power verification products, Synopsys

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