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Iterative into interoperative

Complex fpgas are driving eda interoperability. By Louise Joselyn.

The traditional design flow – where netlists and schematics are passed to the pcb layout team – is proving inadequate for designs involving complex fpgas, particularly in large pin count bgas.

Even before signal integrity and thermal management raise their heads, designers often find functional, physical and manufacturing inconsistencies between fpga and board that need resolution. Increasingly, the only viable system solution requires a concurrent and iterative approach, with interaction between fpga designer, logic designer and pcb layout expert and their tools.

Mentor Graphics is one eda vendor addressing these issues. Product manager David Brady said: "Typically, the fpga designer does not have access to critical board level electrical data. Having some idea of the board topology is essential when assigning the physical location of fpga signals."Brady further points out that use of the automatic pin number assignments provided by the fpga vendor's place and route tool will generate a near random definition. Such a 'hands off' approach can lead to disaster, he warns.

Given that a major attraction of fpgas is flexibility and that device interfaces can be easily reprogrammed, an iterative design approach becomes the norm.

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Graham Pitcher

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