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New Electronics roundtable: Industry collaboration the name of the game as comms links get faster

  • Brad Griffin, product marketing director, Cadence
  • Trevor Smith, product marketing manager, Tektronix
  • Gary Hinde, sales application engineering manager, Cadence Design Systems
  • Eric Spooner, business development manager, Intersil
  • Bob Blake, product and corporate marketing manager, Altera Europe

Communications links are getting faster. Where designers once worked in the Mbit/s range, the latest standards are moving data rates in the Gbit/s arena; to 11.5Gbit/s and beyond. Creating products which shift data at those rates is a challenge.

Almost inevitably, such a product will be built around an fpga. But there's also signal chain issues to be considered and a pcb will have to be designed at some point. And when the product is made, it's got to be tested. All of these aspects compound the problem.

Looking to discuss these issues, New Electronics brought together experts from each sector to outline how their companies are helping those hoping to design such products.

We asked you about high speed design issues. About a quarter of respondents expect to start a design featuring high speed communications within the next year, with many looking at PCI-Express and at 10G Ethernet. More than half said their knowledge was not as good as it could be.

But what did those with experience of the sector find most difficult? Topping the list of problems were pcb design and test and measurement. And what did they want? More web based support, better design tools, more reference designs and application notes.

What did our experts have to say? All agreed that pcb design was one of the most important issues. They also believed there was a need for more accurate models and for better design tools to foster collaboration.

Bob Blake, product and corporate marketing manager for Altera Europe, noted: "It's important for designers to understand signal levels and what a pcb can do." He also noted the need for better models, but pointed out that 'careful design' is also needed. "There are some things that we, as fpga vendors, can do, but it's often down to good pcb design."

Gary Hinde, sales application engineering manager with Cadence Design Systems, pointed to the steps in the design process. "Everything from specification to manufacturing. Within that flow, a change to the board layout may flow back to change the spec or the fpga pin out." His solution? "Design reuse and modular designs. I have UK customers whose boards can contain up to 80% of reuse. However, their challenge is the interface between the blocks. Design will never be completely modular, but it does help to solve problems."

Brad Griffin, a product marketing director with Cadence, added: "We work with semiconductor partners to provide reference design, but customers often want something different; fewer layers, for example. A lot of what we've done is addressing that – cut and paste, for instance – but designers need to check against the high speed constraints."

He added that many designers want to work at higher levels of abstraction. "Relationships need to be built together if design work is to be reused. But everyone has less time for design, which means more intelligence is needed in the design flow."

Hinde continued: "Design intent is key and this should always be based on performance. You should use a standard as a reference or work from a design in kit."

Blake wondered how much time could be saved. "On more complex boards," said Hinde, "it could be six to eight weeks, but this assumes up front investment in creating models. PCB designers are good at making their designs fit requirements."

Speaking to the signal chain part of the puzzle, Eric Spooner, business development manager with Intersil, said: "High speed interfaces are pushing into the industrial world. High speed a/d converters are a good example at a high level of how interfaces are changing and the design flow issues involved."

He outlined how a/d converter interfaces had changed over the years. "LVCMOS was good to about 250Mbit/s, but needed 16 traces. Serial lvds took data rates to about 1.2Gbit/s, reducing the number of traces to 10. Now, serdes has pushed the data rate to 11.5Gbit/s while needing only two traces. Fewer traces might mean less timing constraints for the designer, but it's now an rf challenge. It's a new problem for a lot of people."

Griffin said: "We used to use simple field checkers and have accuracy beyond the date rate; to 4GHz, for example. We never imagined signals would get that fast. Now we need different techniques, including S parameters, and we need full wave solvers to get higher accuracy. Implementing the interconnection might be simple, but modelling is more complex."

Spooner pointed to JESD204, the standard covering interconnection of a/d converters and logic devices. "All major converter and fpga manufacturers are on the sub committee. While version A had a maximum data rate of 3.125Gbit/s, revision B pushes this to 11.5Gbit/s. Designing to this means there must be an up front focus on simulation and signal integrity. If the link doesn't work in the lab, you won't be able to debug it without going back to find out what's wrong."

Blake said: "Customers now expect a reference design and demos with partners. They don't have the time and are looking for solutions."

With the discussion moving on to test and measurement, Trevor Smith, product marketing manager with Tektronix, pointed out the effect of higher speeds on the timing budget. "When you move from 5Gbit/s to 8Gbit/s, the timing margin is cut by 40%; and a smaller timing budget is the first of many problems, including noise, interference, crosstalk and jitter."

From the test perspective, Smith said it's all about following standards. "There are different standards, each with different measurement points. The designer needs to deliver signals of different quality to particular points. The tricky bit is what goes on in the middle."
Equipment is an important part of the puzzle. "Once, you looked at a 1Gbit/s signal and wanted a scope that would capture the fifth harmonic, so you used a 5GHz scope. Now, the dominant spec is rise time."

He noted that rise time and bandwidth used to be related, in that rise time was always assumed to be 0.35 bandwidth. "At higher rates, that breaks down," he said. "It's rise time that dictates whether you can measure the eye or not."

He also counselled users to beware of noise injected by the scope. "Equipment can use up your noise budget."

Hinde wondered about the effect of product miniaturisation on test points. "What's the biggest challenge?" he enquired.

Smith said it was a problem. "Not all standards require test points," he said, "but PCI-Express, for example, demands them."

Spooner asked whether test points impacted the signal being measured. "It's not something you'd choose," Smith continued, "but you have to be able to test."

Asked why he thought New Electronics' readers saw test and measurement as one of the biggest problems when it came to high speed design, Smith implied that designers expected problems before they appeared. "So, if you expect a problem, you plan ahead. Once you've done that, you've eliminated a conceptual problem."

The experts at the roundtable agreed that collaboration amongst suppliers would be of increasing importance if designers were to meet shrinking design cycles and growing technical challenges.

Summing up, Blake said: "High speed design is challenging. Designers need a strong ecosystem to ensure success, and that includes knowledge, tool flows and high quality test equipment."

The High Speed Design roundtable was sponsored by:
Altera
Cadence
Intersil
Tektronix

Participants:
Brad Griffin, product marketing director, Cadence
Bob Blake, product and corporate marketing manager, Altera Europe
Gary Hinde, sales application engineering manager, Cadence Design Systems
Eric Spooner, business development manager, Intersil
Trevor Smith, product marketing manager, Tektronix

Author
Graham Pitcher

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