03 February 2011

End to end flows are set to reshape ic design

Providers of electronic design automation (EDA) software have typically focused on individual point tools, or on collections of tools aimed at a specific design domain, such as analogue or digital physical implementation. It's time for a broader view that looks across traditional design domains and includes everything needed to solve a specific technology problem.

There are four technology challenges that need comprehensive solutions: gigagate/GHz digital designs; low power designs; mixed signal designs; and 3D ics with through silicon vias (TSVs). Cadence Design Systems has recently announced an end to end digital flow that addresses each of these challenges.

An 'end to end' flow is one that cuts across traditional design domain boundaries and provides a complete solution, resulting in a cost effective, manufacturable electronic component. Thus, the new Cadence digital flow not only provides improvements in traditional placement and routing tools, but also in logic synthesis, engineering change order checking, timing and noise analysis, low power design, analogue and mixed signal integration, and ic/package codesign.

The underlying principle behind this flow is called Silicon Realisation. Part of the EDA360 vision, Silicon Realisation has three requirements. One is a unified representation of design and verification intent that is carried throughout the flow. Another is the appropriate use of different levels of abstraction to enable improvement in runtime, accuracy and capacity for designs of various sizes. The third is convergence with physical and manufacturing data, resulting in a finished design that can be taken into manufacturing.

Cadence has developed some new technologies that support these requirements throughout the end to end digital flow. For example, to ease gigagate/GHz digital ic design, a new data abstraction technology has been developed that can model blocks with millions of instances simply and accurately, improving runtimes by as much as twenty times.

A new analysis engine speeds digital ic convergence by combining timing and noise analysis into a single step, rather than running two steps and merging the results back together. This engine can result in 2X faster closure for timing and noise. Physically aware logic synthesis that involves floorplanning and considers cell placement information during synthesis is yet another capability that improves convergence in the design flow.

Cadence already offers a constraint driven mixed signal design flow that leverages both the Encounter Digital Implementation System and Virtuoso custom design environment. That constraint driven flow has been enhanced, allowing a consistent representation of design intent for analogue and digital design teams. For example, the same differential pair routing constraint can drive analogue and digital routers.

To support advanced low power designs, Cadence has introduced a new power intent 'architect'. With support for the Silicon Integration Initiative's Common Power Format (CPF) and Cadence's commitment to power format interoperability, the power intent architect provides an easy way to define and validate power intent throughout the entire digital flow, with an intuitive and easy to use graphical user interface. In addition, hierarchical macro model support for power intent lets silicon IP providers supply power domain intent information without revealing the internal circuitry in the IP block.

Finally, the new flow includes a comprehensive 3d ic design methodology. This allows designers to express intent with a stacked die editor. They can then run 3d aware floorplanning and routing using an abstraction of the adjacent top and bottom die, thus having an awareness of the TSVs and microbumps on those surfaces without needing the entire database for each die. IC/package codesign allows convergence into a manufacturable stacked die package.

End to end flows that support unified design intent, abstraction and convergence will become increasingly vital as ics and electronic systems become more complex. They will make advanced node digital and analogue designs possible, make designs at mature process nodes more cost effective and bring emerging technologies such as 3d ics to mainstream designers.

Author profile
Wei Lii Tan is a senior product marketing manager with Cadence Design Systems.

Wei Lii Tan

Supporting Information


Cadence Design Systems Ltd

This material is protected by Findlay Media copyright
See Terms and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the sales team.

Do you have any comments about this article?

Add your comments


Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

Altera gets 14nm test chips

Altera ruffled some industry feathers in February 2013 when it announced that ...

Hardened DSP blocks for FPGAs

Responding to the increasingly demanding task of designing floating point DSP ...

Fine pitch Cu bumps used

Altera says it is the first company to adopt TSMC's fine pitch copper bump ...

Interconnect: Polymer fibres

Fibre optics are good for transmitting high speed data across the Atlantic, but ...

Industrial electronics

The Carbon Trust has estimated that 40% of global electricity consumption is ...

In-flight electronics get OK

Many will feel vindicated, others surprised and a few sceptics will still be ...

NI Trend Watch 2014

This report from National Instruments summarises the latest trends in the ...

Mobile OS architecture trends

In this whitepaper, Intel describes its investigations in the trends of mobile ...

A better way to cloud

This whitepaper explores the factors around the shifts in cloud computing, and ...

Low profile UARTs

Exar has introduced two UARTs for the Intel Low Pin Count (LPC) motherboard bus.

High speed CAN transceivers

Looking to help system designers achieve compliance with stringent industrial ...

Modular power supplies

While engineers are increasingly looking to simplify power design, often by ...

Future World Symposium 2014

29th - 30th April 2014, Twickenham Stadium, London

Device Developers' Conference

20th May 2014, Holiday Inn, Bristol

Device Developers' Conference

22nd May 2014, Menzies Hotel, Cambridge

DLP 0.45 WXGA chipset

Learn all about the features and benefits available to developers with the DLP ...

Electronics Design Show 2013

Take a look at some of the highlights from the 2013 Electronics Design Show and ...

Industrial automation software

TI continues to enhance its software offerings for the industrial automation ...

Smartwatches and Sir Clive

All the excitement about smartwatches brings to mind the Sinclair Wrist ...

You will buy a smartwatch

The announcement yesterday by Google that it is extending Android into the ...

Sony’s slide continues

Not so long ago, if you asked the legendary 'man in the street' which consumer ...

Neelie Kroes, EC Commissioner

"The objective is to ensure that the semiconductor industry in Europe has the ...

Gregg Lowe, Freescale

Freescale's new ceo tells Graham Pitcher that, while he's not 'dancing' yet, ...

Menno Treffers, WPC chairman

There are now 110 consumer electronics products that are authorised by the ...