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Easing design effort

Simple hardware and software interfaces reduce a/d converter design effort. By Mark Thoren and Steve Logan.

With high accuracy and high noise immunity, delta-sigma a/d converters can measure many types of sensors directly. However, high precision sensors often have a large inherent impedance value and input sampling currents to the a/d converter can overwhelm high source impedances or low bandwidth, micropower signal conditioning circuits.
The problem arises due to the switched capacitor input structure of delta-sigma converters. Capacitors are toggled at up to 10MHz between the input, reference and ground as a function of the final output code. Each time these capacitors are switched to the input, a current pulse is generated. A pattern of charging/discharging pulses is seen at the input pin of the a/d converter. This pattern is a complex function of the input and reference voltages. External RC networks, high impedance sensors and micropower amplifiers that do not settle completely during each sample period cause large dc errors.
The trick to solving this problem is to take advantage of the oversampling properties of delta-sigma converters. The front end capacitor, switching on a per sample basis, is identical to conventional delta-sigma converter sampling. Linear’s Easy Drive front end sampling architecture controls the switching pattern of the capacitor array. When summed over the entire conversion cycle, the total differential input current is zero, independent of the differential input voltage, common mode input voltage, reference voltage or output code. The common mode input current is constant and proportional to the difference between the input common mode voltage and reference common mode voltage.
Much of the complexity around the a/d converter – such as external components and software timing – is gone, saving design and test time.

Author
Mark Thoren and Steve Logan

Related Downloads
14681\Easing Design.pdf

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