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Designers take a fresh look at power management system design

Designers take a fresh look at power management system design

As programmable logic technology migrates into the power subsystem portion of a design, new capabilities are becoming available to engineers. The benefits of applying programmable logic technology to power management are realised when designers can step back and take a new look at the design, using PLDs as high level system components to create more integrated solutions.

One way to illustrate this 'design mind shift' is with an example. The target is a power/board management subsystem for a control card in a rack mounted communications system. The board has a CompactPCI Express (cPCIe) backplane that can be inserted or removed while power is applied (hot swap).

The backplane supplies the standard cPCI Express power supplies of +12V, +5V and +3.3V, and these can be used to develop additional voltages (for example, +2.5V and 1.8V). Here, the 12V rails will provide the bulk of the power to the board with point of load (POL) dc/dc converters for +2.5V and +1.8V.

The subsystem has the following requirements:
• Board power can range from 10W to 200W.
• When inserted into a system with power on, the +12V, +5V and +3.3V board rails need to be brought up in a controlled manner.
• The board must generate a backplane fault early warning.
• Voltages must be sequenced properly.
• Board specific power management signals must be generated for fpga initialisation, device and subsystem resets.
• Backplane voltage measurements and onboard voltage and current measurements must be made available to the system controller via i2c.

Bottom up design
A designer might find it tempting to place familiar circuit elements into the power management subsystem. Using devices like hot swap controllers, a power supply sequencer/monitor, dc/dc converters and mosfets, the designer can begin developing parts of the design, while adding other components to implement new features. Invariably, a PLD will be added to connect some devices and to sweep up remaining digital functions needed to implement part of the cPCI Express control signals.

However, this approach can increase cost, reduce system quality and reliability, while increasing the risk of board respins. Since each power management function is designed without considering the others, devices may be duplicated unnecessarily. Additionally, as each device is designed in isolation, they have their own sub components and these are duplicated. Apart from increasing costs, reliability will also be reduced, due to more components and interconnections.

The most important thing a power management subsystem can do is to improve supply fault monitoring accuracy and thus shutdown speed. If faults are responded to accurately and quickly and swift corrective action taken, damage to the on board components is minimised. A bottom up design approach will create a non uniform system, with overlapping implementations and with accuracy and response time possibly degraded.

For example, if the supply has not had time to react to a card extraction, it may not be possible to provide an early warning to the processor and enable orderly shutdown. Similarly, it may not be possible to adjust various timing components to provide the critical interdependent delays for debounce, retry period and reset sequencing.

No matter how careful a designer is, there is always a risk that changes will need to be made after the board has been made and a power management design that uses individual fixed function components will probably require a respin.

Top down approach
In contrast, the top down approach begins with a review of the system's key power requirements. Rather than selecting power management components, the designer selects an integrated programmable power management device that includes the functions needed to satisfy those requirements.

The power management device (see fig 1) will contain many of the parts that would be used in a bottom up design, but they are integrated in one device and organised functionally to simplify the design process. Two of these functional blocks will be used to better illustrate this methodology shift from component thinking and bottom-up design, to functional thinking and top-down design.



The dual threshold power supply monitor creates two outputs: a threshold (greater than RefA) and window (between RefA and RefB). Due to its high level of integration, this block can replace many off the shelf supervisors and reset generators. These on chip comparators monitor for supply faults with an accuracy of 0.7% and can generate a fault signal within 16µs.

Meanwhile, the high voltage mosfet driver output either sources current with a specified ramp rate and with a specified voltage level, or sinks a specified current to ground. In Power Manager II, mosfet characteristics are programmable, which allows the designer to modify timing, voltage or current levels. This allows a quick response to changing requirements; for example, if the ramp rate for a mosfet gate voltage needs to be adjusted because one voltage needs to be turned off more quickly than another, this can be done by programming the new rate.

High voltage mosfet drivers are versatile and can control other functions, such as hot swap, power supply ORing or power feed to external cards. This reduces the need for additional components and reduces cost.

These two key functions also work together to simplify parts of the design. For example, the monitor block can be used to sense excessive current during a hot swap, and then the mosfet driver can be used to control the mosfet gate, keeping the mosfet within its safe operating area. Cost reduction may not be possible when multiple separate devices are used, since the signals needed to implement these functions may not be available on external pins or may require additional 'glue.'

Implementation example
A cPCIe power management subsystem using a top down approach is shown in Fig 2. The Lattice Power Manager II is at the core of the design, integrating hot swap control for board rails (using mosfet Q5 for +3.3V, Q4 for +5V and Q1 for +12V via the charge pump circuit); monitoring voltages and currents for faults; sequencing on board voltages (via the +1.8V and +2.5V POL regulators) so the fpga, memory and mcu initialise correctly; turning off the mosfets during a fault or hot swap; and generating resets.



The PLD block creates the required cPCIe bus control signals, board level reset, initialisation and early fault warning signals. It also provides the timing and feedback control needed to control the hot swap mosfets, the enable on the POL supplies, debounce, retry, overvoltage, overcurrent and short circuit protection. The PLD provides centralised control logic that ties together power management functions to reduce design complexity. Finally, the PLD block reduces the risk of board respins, since all the major device, timing and control characteristics can be changed as needed.

This design not only satisfies the key requirements of the cPCIe power management subsystem, it also reduces cost per function, improves quality and reliability and, when changes are needed, significantly reduces the impact to schedules and the risk of board respins.

Shyam Chandra is system programmable mixed signal product marketing manager with Lattice Semiconductor.

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Shyam Chandra

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