26 February 2007
Cutting fpga design time
A more sophisticated approach to reducing fpga debugging cycles. By Joerg Kalita.
For many fpga designs, basic knowledge of the place and routing capabilities of modern pld design tools, as well as a minimum of design preferences, is sufficient to produce reasonable results. But if a critical performance metric needs to be achieved, a more sophisticated approach is needed.
The tools embedded within today’s pld software suites can help save time and money during the design implementation stage. The principles are outlined using Lattice Semiconductor’s ispLEVER as an example.
Design information can be imported from a variety of sources, such as Vhdl, Verilog, schematic entry and EDIF. Preconfigured IP cores, including those from third parties, can also be imported. A Matlab/Simulink interface, along with synthesis and RTL simulation tools from Synplicity and Mentor Graphics (Synplify, Precision and Modelsim), are also provided.
ispLEVER imports data from various sources and constructs a common database. Different netlists can be bound together to handle mixed sources, such as Vhdl and Verilog, in one project – useful when the synthesis tool does not handle a mixed input.
After the database is constructed, the next step involves the Design Planner – the main control for the input of environmental conditions. Users can not only input the usual preferences, such as frequency and I/O timing, but also relevant design information, such as pin placement, driver output, I/O standards and global attributes.
The Design Planner can also be used to check such things as critical paths using the Path Tracer. Paths can be displayed graphically and a Floor Planner is also available. In this way, designers can quickly get a feeling as to whether the pin out is optimal for the design and whether related logic blocks are well placed.
Author
Joerg Kalita
Supporting Information
Downloads
8886\Cutting Design Time.pdf
Websites
http://www.latticesemi.com
Companies
Lattice Semiconductor UK Ltd
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