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Creating flash memories with more bits per cell

Moore's Law is the heartbeat of the semiconductor industry. Driven by its prediction that the number of transistors on a given area of silicon will double every 18 months, the industry has continued to move designs to ever smaller processes.


In general, this approach has served device designers and manufacturers well: fpgas, microprocessors and dram are some of the more obvious beneficiaries of process shrinks.
But there is always an exception that proves the rule. In this case, it's flash memory.
Flash has proved a versatile storage medium, with its non volatility being the main attraction. Because no power is needed to maintain data, battery operating lifetimes are extended. And, although access times are not as fast as dram, flash memory provides read and write times fast enough for use in pcs and portable devices. As such, it's the mainstay of USB sticks and consumer memory cards.
But here's the problem: flash doesn't scale well. Process shrinks, by their very nature, provide less real estate per function and that works against flash. The solution is to increase the amount of information that can be stored per unit area.
There are essentially three ways of doing this: multilevel; multibit; and stacking.
Paolo Cappelletti is vice president, R&D technology development, for Numonyx, the specialist company created by the merger of STMicroelectronics' and Intel's memory interests. He said multilevel flash memory was proven in the 1980s and used originally to store the outgoing message in telephone answering machines. "The concept is simple, but process scaling reduces the design margin and brings a trade off between performance and reliability."
Multibit, as the name suggests, sees more than one bit stored per cell. "This is another technology proposed in the 1980s," Cappelletti continued. Within each memory cell, there needs to be two locations for storing information. "Although it's one cell," he noted, "it's really a series of three devices."
But it's the stacking approach which is becoming increasingly popular as manufacturers look to maximise storage density. The logic of this is that if you can't shrink the design readily in two dimensions, then why not use the third dimension to provide the additional storage?
Cappelletti pointed out two approaches being developed. "In Samsung's case, the company is stacking layers of memory cells one on top of the other. Toshiba, meanwhile, is creating vertical stacks of memory cells in series."
As Cappelletti noted, if you can't get it smaller, then go upwards. "But these are more complex processes and bring trade offs between wafer cost and higher storage density."
Numonyx has more than a passing interest in these developments, having recently announced the first samples of a 1Gbit multilevel cell NOR flash memory created on a 45nm process. According to the company, the move has allowed it to 'significantly increase' the performance of its memory products and points to a 50% increase in write speed over previous generation devices.
Ed Doller, Numonyx' chief technology officer, noted: "The need for high density, low cost NOR flash memory continues to drive aggressive scaling requirements. Numonyx' engineers overcame major scaling limitations by developing new process techniques to produce the seventh generation of multilevel cell NOR flash on the industry's most advanced 45nm technology."

Author
Graham Pitcher

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