11 September 2012
Atmel SAM4 mcu family: it's about more than just the core
The progression towards more powerful microcontrollers (mcus) shows no sign of abating. Indeed, while the traditional 8bit market holds steady in size, sales of more powerful 32bit processors are growing at a healthy rate.
What this indicates is that today's mcus are enabling products that are ever-more complex. The growth has been spearheaded by devices such as the Atmel SAM3 family, based on the ARM Cortex-M3 processor. An increasingly large number of applications, however, demand even more processing power.
The latest in this line of progression is the Atmel SAM4SD series (see figure 1).
Figure 1: Block diagram of the Atmel SAM4SD microcontroller
But delivering the levels of performance required by demanding applications is not just about the capabilities of the core. Emerging products such as building and home control equipment, portable medical appliances, smart meters, and industrial automation/M2M systems are complex.
They almost invariably boast a graphical user interface (GUI) and are Internet-enabled. Software content is high, and the finished product is often of substantial dollar value.
As a result, many systems require the ability to undergo field upgrades during their service life – one reason for the increasing popularity of Flash memory for program storage. And overall, the bus and memory systems that surround the core must be just as carefully designed as the core itself.
Of course, the Cortex-M4 processor produces a significant hike in performance, over and above what can be attained with the Cortex-M3 core. It incorporates digital signal processing (dsp) extensions, including single cycle 16/32bit and dual 16bit multiply accumulate instructions and 8/16bit single instruction/multiple data (SIMD) arithmetic. In addition, the core can be supplemented with a single-precision IEEE754 compliant floating point unit (fpu).
This enables Cortex-M4 processor based mcus, such as the SAM4SD, to implement fixed-point finite impulse response (FIR) processing in 71% fewer cycles than would be needed using a Cortex-M3 processor based product. Where the fpu is selected, floating point operations benefit
even more: for example, floating-point correlation requires 91% fewer cycles (see fig 2). The savings are not just in the reduction in processing cycles: there are also fewer memory access cycles.
Fig 2: A Cortex-M4 based mcu can implement a fixed point FIR response in 91% fewer clock cycles than a Cortex-M3 device when the fpu is selected
The system serves the core
As we have observed, getting the most out of any processor requires careful design of the memory and other surrounding subsystems. The latest Atmel SAM4SD32 devices augment the inherent power of the Cortex-M4 processor with up to 2Mbyte of flash memory: the largest amount of flash available in a low power Cortex-M4 processor based mcu. In addition, the devices are equipped with up to 160kbyte of sram and a 2kbyte cache to accelerate program execution.
The SAM4SD devices join Atmel's SAM7 family, based on the ARM7TDMI, that runs at up to 55MHz, and the SAM3 mcus, based on the Cortex-M3 processor and running at up to 96MHz. Both of these device families can be equipped with up to 512kbyte of flash.
Complex applications need more memory
The most basic benchmark of mcu memory is size. Today's embedded applications are increasingly memory hungry. A product that uses a real time operating system (RTOS) might need to dedicate up to 30kbyte of space to that part of the system alone. A file system might consume a little more than that: perhaps 50k. Likewise, communication stack implementations, such as TCP/IP and USB, generally come in at around 30k to 50k. It is harder to generalise about the requirements for a GUI. These can be implemented in as little as 60k, but this is heavily dependent upon complexity: for example, a 50 x 50 pixel icon requires around 50k and a widget might require 30k.
Commercial third-party implementations of more complex communications stacks, such as ZigBee PRO, require around 128k. Finally, at the top of the range, facilities like multifont support are costly in terms of memory footprint, requiring more than 256k.
Whatever the level of complexity of the application, it is invariably cheaper and simpler to use on chip memory in preference to external components: larger memory mcus also offer a degree of future proofing, allowing new features to be implemented without hardware changes.
Banking on flash
Size is not the only important consideration when thinking about mcu subsystems and memory. One key feature of the SAM4S series of processors is the availability of dual banking within the flash memory (see fig 3).
Fig 3: Dual bank flash provides a fail safe method of implementing remote firmware upgrades
Products ranging from internet equipped tvs to dsl routers and smart utility meters are routinely designed to allow remote firmware upgrades via a wired or wireless connection. Dual bank flash provides a fail safe method of achieving this. The system can download and install the upgrade into Flash Bank 2, while main program execution continues out of Bank 1. When the upgrade is complete, the system can test whether the update has been successful: if not, execution continues out of Bank 1 and the system requests a repeat of the update process. If the update is
successful, execution is switched to Bank 2, leaving Bank 1 available for the next update.
This banking structure has a number of important benefits. First, the system cannot be brought down if a power outage, communications failure or other error takes place during the update process. It also allows the product to continue to function at full capability while the update takes place. This is essential in products that need to deliver 100% availability, such as a smart electricity meter. Such a device must be guaranteed operational all the time.
In the SAM4SD MCU, a specific general purpose non volatile memory bit (GPNVM bit 2) that can be cleared or set via the chip's enhanced embedded flash controller (EEFC) enables switching between the two flash banks. The chip's EEFC itself contains a user interface that is mapped to the chip's advanced peripheral bus (APB).
Security is also a priority
GPNVMs are used for a number of important memory oriented features, including the protection of program IP and other data. Setting the SAM4SD mcu's GPNVM security bit disables access to the flash, sram, core registers and internal peripherals. Subsequently, the security bit can only be unset by performing a full flash erase, via the EEFC's ERASE instruction. This ensures the confidentiality of the code programmed in the flash memory.
The data and control flow between the mcu and external components can also represent a security vulnerability. The SAM4S series, in common with previous SAM3 devices, includes a scrambler function within its external bus interface (EBI). This can be used to encrypt communication between the SAM4 and external devices, without access penalties.
The device also features a memory protection unit (mpu) that places a 'firewall' between the firmware code modules for different applications, and prevents the execution of firmware running in privileged mode from external memory.
Subsystems impact speed
The design of the memory system has a significant impact on overall mcu performance. The SAM4S series provides zero wait state operation out of flash at 120MHz, yielding a CoreMark/MHz performance of 2.14. As an example of the resulting performance levels, this allows 128bit AES encryption to be performed in software at data rates of up to 13Mbit/s.
As well as enabling zero wait state operation, the mcu's internal bus structure has a major impact on overall execution speed. If there are insufficient on chip communications facilities, an internal bottleneck can result, starving the core of the data it needs for program execution.
The SAM4SD device features a multilayer bus matrix, multichannel direct memory access (dma) and distributed memory to support high data rates.
The bus matrix creates direct pathways between the various data channels and multiple on chip memories, including the buffers on the usb and EBI. The dma architecture supplements the central dma channels with compact dma controllers dedicated to the bus interface of each on-chip peripheral. This strategy effectively removes the entire data transfer load from the cpu. Finally, the distributed sram configuration includes two central memory banks and two 4kbyte buffers in the on chip usb port and EBI, permitting parallel data transfers.
Tools are essential
All of these features are of little avail if the designer can not use them effectively. To solve this problem, Atmel supplies a wide range of tools including the Atmel Studio 6 integrated development environment (IDE), with integrated Atmel Software Framework. In addition to a full GNU C/C++ compiler, an editor, linker and debugger, this provides more than 1100 ready to use projects, including source code that can be used to give engineers a head start with their designs.
The Atmel QTouch Composer facilitates the development of capacitive and resistive touch interface applications, while compact, low cost SAM4S Xplained evaluation kits allow designers to initiate and run basic applications quickly and simply.
Today's embedded applications require all of the processing power that modern cores like the ARM Cortex-M4 can deliver. Increasingly, the surrounding on chip system and supporting design tools are as important as the choice of cpu in ensuring these capabilities are fully exploited.
Atmel's SAM4SD mcu provides a combination of features aimed at these applications, including the industry's largest complement of on chip flash memory, dual bank organisation for field upgrades, on chip security, a rich internal architecture and comprehensive hardware/software support.
Such developments allow designers to make full use of the capabilities of the Cortex-M4 processor, maintaining the inexorable march towards increasing complexity that continues to be the hallmark of the microcontroller market.
Jonathan Page is with MSC Gleichmann