14 June 2011
Advanced chip manufacturing: Larger wafers, smaller features
When Gordon Moore developed his eponymous law, he focused only on the number of transistors that could be accommodated on a given area of silicon; the size of the wafers on which devices were fabricated was not a contributory factor.
But as feature sizes have shrunk from a handful of microns to a handful of nanometres, the wafers on which devices are created have grown in diameter. Today, mainstream semiconductor manufacture is based on 300mm wafers. Now, TSMC, Intel and Samsung have announced they're ready to move production to 450mm diameter wafers.
But it's not just a question of whether to use 300 or 450mm wafers; there remains the immense technical challenge of meeting the scaling requirements of Moore's Law. The move to each new process node involves huge technical complexity and investment. Together, these challenges are concentrating minds across the industry.
Malcolm Penn, chairman of market watcher Future Horizons, has seen many such moves during his four decades in the semiconductor industry. He said that only a few months ago, the industry was asking if it would move to 450mm. "Now, it's when," he claimed. "But the interesting thing is that the industry has determined that the transition to 450mm should be done properly, not like the move to 300mm. So there is an attempt to orchestrate equipment suppliers in tandem with industry leaders and followers."
But it's clear the transition to 450mm wafers isn't going to happen overnight. Talking to New Electronics earlier in 2011, Maria Marced, president of TSMC Europe, said: "We have firm plans to build a 450mm pilot line in Fab12 phase 6, which will start with 20nm devices in 2013/2014. Volume production will be in Fab 15 in 2015/2016."
TSMC is moving to 450mm wafers simply because of the economics. Marced said: "Everything about 20nm is expensive. We have to go to 450mm wafers, otherwise it will be extremely difficult to make the business case."
But the 450mm question is also exercising the European Commission (EC), which is currently wondering whether or not to provide support to European companies for the move. Penn is in the process of compiling a report, due to be delivered later in 2011, which will investigate, amongst other things, whether the EC should finance the building of a 450mm fab in Europe. "If this happens," Penn remarked, "one of the questions is what do you fill the fab with. But that's an issue that will be explored in the report."
Europe has already started to examine the issues through EEMI: the European 450mm Equipment and Materials Initiative. Bas van Nooten, director of European cooperative programs with semiconductor process equipment specialist ASM International, speaks for the Initiative. He said the Initiative started in 2009. "The EC called a meeting – mainly of SEMI members – to find out what we thought about 450mm. During the meeting, it became apparent from the equipment side that something should happen; that we should start work so that Europe could be early. We were quite surprised with the level of enthusiasm and work started early in 2010."
EEMI, which has around 40 members, has been designed to form part of the European ENIAC programme. "This has many advantages," van Nooten said. "EEMI fits the ENIAC context and we entered an outline proposal, which has been accepted." The 21month project has received funding of around €12million.
EEMI is focused on the equipment industry, a sector in which Europe has traditionally been strong. "The European equipment market has a large market share around the world," van Nooten pointed out, "and companies joining the project are looking at global sales."
Part of the motivation behind EEMI is for Europe to be ready to supply 450mm production equipment. "Intel, TSMC and Samsung are already customers of European equipment suppliers and we not only want to keep them as customers, but also to grow Europe's market share in emerging technologies."
Penn believes the transition from 200mm to 300mm production wasn't handled properly and van Nooten concurred. "Then, the transition was paid for by the equipment industry; this time, we want to get the semiconductor industry involved. Before, tools were provided free of charge; now, semiconductor companies are helping in development of 450mm technology."
A similar initiative is underway in the US, where ISMI – the International Sematech Manufacturing Initiative – is working on 450mm technology.
Recently, ISMI announced that it is moving its work to the College of Nanoscale Science and Engineering at the University of Albany. An investment of $20m from the State of New York in its 450mm programme will increase the supply of 450mm silicon, amongst other benefits.
Reluctant to comment directly on its 450mm work, ISMI's website says that test wafer development has started and that interest in equipment development is increasing around the world. It adds that silicon suppliers are positioned to provide additional quantities of 450mm wafers and that 450mm equipment platforms are now available. In particular, it says the crystal quality of 450mm wafers is 'in better shape than the 300mm wafers were at the same development stage'.
While wafers are getting larger, feature sizes are getting smaller; and that presents another set of problems for equipment manufacturers. Klaus Schuegraf, chief technology officer of Applied Materials' silicon systems group, outlined some of the challenges.
"There is a tremendous increase in complexity as we move to advanced technology nodes, with points of inflexion in four areas: transistors; interconnect; patterning; and packaging."
One of the biggest changes is at the transistor level, where the move to 20nm and beyond is seeing a complete redesign of the building block for electronic devices. "It's high K metal gate (HKMG) after 20nm," Schuegraf asserted. "But two different solutions to the problem have emerged. Beyond this," he continued, "the long term will see 3d devices."
Metal gate transition is in its infancy, said Schuegraf. "Over the next three to five years, there will be a big roll out. Intel has already deployed the technology and TSMC, GlobalFoundries and Samsung are in the early stages, driven by the need to develop high performance devices."
Schuegraf said these points of inflexion are highlighted by the increased spend on fab equipment. "As we move down the technology curve, we're seeing a significant increase in capital intensity. At 20nm and beyond, there will be a healthy uptick in spending; and that's all down to complexity."
HKMG is seeing two approaches: 'gate first' and 'gate last'. "TSMC has a similar approach to Intel," he said, "adopting 'gate last'. IBM, meanwhile, had been pursuing 'gate first', but has switched to 'gate last' for its 20nm process."
He explained the problems. "The conventional way of building a transistor, using an oxide poly gate, requires five manufacturing steps, with three of these for building the SiON gate dielectric. This allowed for growth and nitridation. But HKMG needs additional steps, because there's the insertion of high K materials, such as HfO2. Then it gets interesting."
Schuegraf noted that metal gate technology is complicated. "There are significantly more metallisation steps and we need to use chemical mechanical polishing (CMP) to define the structure, as etching is no longer a good approach."
The 'gate last' transistor process starts with a dummy gate, followed by the etching of connections. Then layers of dielectric are laid down until they reach the top of the dummy gate. "We then remove the dummy," Schuegraf continued, "and put the real gate dielectric into the channel, then lay down the multilayer metal stack."
Isolating the metal stack and the high K materials could be done using an etch process, but Schuegraf claimed this was difficult to control and that CMP was 'simpler'. "But we're asking CMP to do something it hasn't done before. It requires an enormous degree of precision." In fact, the process requires an accuracy to a thickness of approximately 10 atoms. "There is a lot of sophisticated metrology to enable end point control and the process requires very precise linearity across the wafer; engineering the system is critical."
So HKMG requires 15 steps, rather than five. "Many of these steps require single wafer vacuum deposition," he said, "with three important technologies: plasma oxidation; chemical vapour deposition; and atomic layer deposition. There are different ways to do things, depending on the needs of the structure, so you have to find the right set of deposition techniques."
Lithography is another problem area. "It's getting quite interesting," Schuegraf said, "with double and quad patterning in some cases. These additional steps need extended precision at each layer; not only improving the performance of conventional technology, but also working on emerging technologies."
Despite these efforts, there is still a limit to scaling. "It's an exciting time to be a semiconductor engineer," Schuegraf believes. "It's not just about making things smaller, it's also about going into 3d; exploring a new degree of freedom."
One of the techniques being applied is the through silicon via (TSV) and Schuegraf sees great potential for this. "It brings the ability to drill through a wafer and to connect them using copper studs. Now, one pin connects as many as 1000 did, but it does require a rethink on packaging. TSV allows for massive parallelisation and better bandwidth."
While European equipment manufacturers are looking towards 450mm, there isn't the same enthusiasm amongst European semiconductor companies and researchers. This group is looking to follow the 'More than Moore' approach; integrating diverse technologies onto silicon wafers using existing equipment. If you are a 450mm fan, you're more likely to be following the 'More Moore' route; pure scaling. "450mm could leave European chip companies behind," said Penn, "because they are happy to stick at 300mm; they generally want to move laterally."
Penn sees the EC facing a dilemma. "Does the EC throw the equipment industry to the wolves because European chip companies say it's not their strategy, or does it move to establish a European 450mm foundry? The EC wants to keep advanced semiconductor manufacturing in Europe, but 300mm is not advanced," he concluded.
Illustrating the dichotomy, Luc Van den hove, president of Belgian research centre imec, told a recent SEMI meeting in Brussels that imec plans to build a 450mm pilot line to enable it to maintain its process research. He also believes that if Europe doesn't have a 450mm fab, then all chip production will move elsewhere. "We are asking the EC to recognise the semiconductor industry as strategic," he said, "but 450mm is not a strategic matter at the EC level."