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Outlook 2011: A new vision for the EDA industry

A new vision for the EDA industry

The electronics industry is shifting its focus from silicon to software applications. It's time for a new EDA approach that puts applications first.

While economic conditions for the electronic design automation (EDA) industry improved in 2010, many challenges remain on the horizon. The EDA industry has been locked into virtually flat growth for the past several years. Average selling prices are declining as pressure for discounting grows and customers increasingly regard EDA as a tactical, rather than strategic, purchase. The EDA industry is on a path to gradual decay and irrelevance unless a dramatic shift takes place.

The problem is not that EDA has changed, nor that EDA tools and services no longer offer value. The problem is that the electronics industry has changed its value proposition from silicon to software applications, changing dramatically the demands placed upon EDA customers. The Apple iPhone has been a major driver here. While electronic products in the past were sold on a one time basis, with no revenue recognition after the sale, Apple pioneered a new business model that allows it to recognise revenue from 'apps' that are sold continuously.

Other providers are taking note. If you buy a large screen tv, the chances are you won't turn it on when you get it out of the box – you'll boot it up. It will very likely come with applications such as Netflix or Pandora and the option to buy more. With entertainment systems and GPS capabilities, cars are also becoming applications platforms. Today, nearly every systems company is looking to change to a business model in which they are constantly making money through applications.

As a result of this trend, systems OEMs are placing new demands on their semiconductor suppliers, telling them that just delivering silicon is no longer enough. Today, they must deliver hardware/software platforms ready for applications development. In 2011, silicon providers will be increasingly called upon to deliver entire software stacks below the applications level, including drivers, an OS and middleware.

Meanwhile, semiconductor suppliers are grappling with a huge increase in the cost of design, especially when software is brought into the picture. The analyst firm IBS predicts that an SoC development project at the 32nm process node will cost $100million, with software comprising about half of the cost. Faced with such costs, many semiconductor companies are shifting their focus from design creation to design integration using prebuilt, preverified blocks of silicon IP.

Traditionally, the EDA industry has only addressed silicon, assuming that chips will be designed first and that software and applications will be appended later. The time has come to turn that approach on its head. That's why Cadence published the EDA360 vision paper earlier this year. With EDA360, design teams start with an understanding of the software applications that will run on a given platform, define system requirements and then work their way down to hardware and software IP creation and integration.

In short, EDA360 is an approach in which the application – not the silicon – comes first. It has three primary areas of focus: system realisation; SoC realisation; and silicon realisation. It's important to note that EDA360 is a vision for the entire electronics industry, not just a Cadence product roadmap or marketing plan.

System realisation
System realisation is the development of a complete hardware/software platform that will provide all necessary support for end user applications. To make system realisation possible, application development must start well before the hardware design is complete. How can we apply virtualisation that makes this possible? The answer, so far, has come from a technology called 'virtual prototypes' (or 'virtual platforms').

Virtual prototyping companies have been around for several years, but they haven't been very successful or profitable. There are several problems with virtual prototyping offerings to date. One is that most have been based on proprietary business models – if you buy the technology from a given company, you're locked into its models. Another is that models must offer both high quality and extremely fast execution speeds, and such models are difficult to develop.

A third problem is the lack of a pathway to implementation. The models used in virtual prototypes today are rarely used in hardware design and verification. A promising new technology that will help close the gap in 2011 is high level synthesis, due to its ability to generate automatically a variety of RTL micro architectures from SystemC transaction level models.

Virtualisation will involve not one solution, but a spectrum of solutions offering various levels of speed and accuracy. Emulation and acceleration will continue to be crucial for their timing accuracy and fast bring up speeds. FPGA prototypes can be employed when extremely fast execution is needed. Throughout the virtualisation process, open standards, such as the Open SystemC Initiative TLM-2.0 are critical.

SoC realisation
SoC realisation is the completion of an individual SoC. In Cadence's definition, this also includes 'bare metal' software, including drivers and diagnostics. This is because software applications must have visibility into what's happening in the hardware and, ideally, direct control over hardware resources. Thus, the applications must connect to drivers in the various IP subsystems, whether that is a memory, CPU, processor or customer specific subsystem.

To realise this, we must change the way in which IP is delivered. In 2011, customers will see IP 'stacks' that include synthesisable IP, 'hard' analogue/mixed signal macros, verification IP, design constraints and driver software for protocols such as USB 3.0. These IP stacks will be 'integration ready' and will thus address a huge inefficiency in the supply chain. Today, we're told, customers are spending up to $5 to integrate every $1 of IP they buy. Wouldn't it be better to spend $2 to buy integration ready IP and skip the added integration expense?

Another requirement is an integrated design environment that allows design teams to run architectural analysis and to source or develop integration ready IP. A third requirement is the availability of design services. Every capability that goes into SoC realisation must be based on open standards.

Silicon realisation
This is at the heart of what EDA does today – but it's under siege and is poised for change. Until now, the EDA industry has focused almost exclusively on design creation. But the focus is shifting to both creation and IP integration – and tools and capabilities are needed for both.

There are many well known and much discussed problems in silicon realisation: low power design, analogue/mixed signal implementation and verification, high performance at advanced process nodes and manufacturability are among the most worrisome. Cost of design, cost of silicon and time to market are also challenging semiconductor providers, leading to a growing 'profitability gap.'

There are three imperatives for effective silicon realisation. One is unified design intent across the entire design and verification flow, including analogue/mixed signal. Another imperative is a higher level of abstraction in order to boost productivity, slash time to market and save costs. A third imperative is design convergence, which includes IC/package codesign and optimisation, system component estimation and analysis, and in design electrical and physical signoff.

However, no single company can implement the EDA360 vision. Instead, it will require a broad, global collaboration, including EDA vendors, customers, IP providers, foundries, embedded software companies and many other players. If we can come together around a broader vision, leverage open standards and meet the challenge of today's application driven system designs, the EDA industry will once again prosper.

John Bruggeman is the senior vice president and chief marketing director of Cadence

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John Bruggeman

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