29 June 2011
3d chip packaging set to enable increased integration
Market researchers are predicting it, chip makers are agreeing to it, some oems are doing it, so it must be true. The 3d chip packaging trend is growing and will have a widespread impact. Not only are there distinct performance advantages to adopting some of these emerging technologies, but the option of continuing as we were, will become increasingly difficult.
3d chip packaging technology embraces a range of solutions. Some – such as bumping, flip chip and chip on board – have evolved from the original multichip module (mcm) approach, including bumping, flip chip and chip on board. Alongside systems in package (SiP), emerging 3d solutions, according to packaging specialist Insight SiP, are at the wafer level and include through silicon via (TSV), embedded components in wafer level packaging (eWLP) and direct stacking.
The somewhat 'clunky' mcms of two decades ago – even stacked bgas of a few years back – have given way to ultra small, low profile solutions. Michel Beghin, Insight SiP's ceo, said: "Size is no longer an issue: complex SiPs are now regularly integrated into smart cards."
But while TSV techniques are becoming popular, primarily for stacking homogeneous devices, other approaches are being developed for heterogeneous chip packaging. French company 3D Plus, a spin off from Thales, has acquired the reconstituted wafer process (RWP) from Freescale and now offers a wireless die on die (WdoD) packaging solution.
By stacking 10 known good rebuilt wafers per mm, it has developed solutions with customers such as NXP, for high density medical applications such as micro miniature endoscopy cameras (2.6mm^2) and devices for pacemakers and hearing aids.
Allain Bouffioux, a senior system architect with NXP, commented: "We are having to add more analogue, transducers and smart sensors to chips, for tasks such as environmental monitoring and energy scavenging." For the oems, heterogeneity is key as rf, antennas, mems, batteries and power management solutions need to be integrated with memories and processors.
STMicroelectronics is looking to integrate not only the electronic (image processing) circuitry, but also embedded substrates, optics, mems gyro and plastics. An example is a vga camera module which has evolved from a 1cm^3 package in 2002 to a 0.02cm^3 package in 2008. TSVs have been used to integrate the lens and sensor with the electronics.
Yves Leduc from Texas Instruments commented that increasingly, the end customer is deciding on package styles. "Clearly package design has become as important as the ic design," he said. "But cost is still a fundamental factor." He pointed out that stacked chips are not always ideal for high performing processors because of heat dissipation issues. "But SoCs are running out of gas," he said. "SiPs can be good for low power designs that are highly heterogeneous and they can be cost effective for limited volumes."
The next stage for TI is to split analogue and digital circuitry into separate stacked die connected through TSV. A carefully designed 3d stack also lends itself to design reuse, Leduc pointed out, as each layer can be updated independently and optimised. "The battery and other components will be integrated later," he forecasts.
Both TI and NXP would like to see standardised approaches to heterogeneous stacked die techniques. One company working towards offering just such an approach is Amkor Technology, which has been working on a PoP (package on package) solution. "This could have stacked die in the bottom layer of the package with high performance circuitry on the top," suggested Moody Dreiza, the company's senior product manager.
He sees an opportunity for this type of application specific packaging approach over a pure custom stacked die package. "For oems, PoP provides a differentiated solution that can be optimised for the application." It offers greater flexibility and potentially faster time to market, than a custom design. "Although it may be slightly higher profile," Dreiza admitted.
Meanwhile, Leduc reckons 3d packaging will bring a fundamental change in the structure of the supply chain. Market researcher Yole Développement agrees and asks 'will the industry be ready?'. Yole predicts the SiP market will grow at more than 15% annually between 2010 and 2015 and that a significant driver of this growth will be 3d packaging. SiP (at $4.5billion) currently represents 15% of the chip packaging market and is set to increase to 24% by 2015. Within the SiP sector, the market for TSV 3d packaging technology will increase from 7% today to 40% by 2015.
In the south of France, the Micro-PackS project, part of the CIMPACA development programme, is ramping its investment in technology, manufacturing facilities and support services. With a combination of industry and government funding and industry and academia resources, the project is designed to build on the region's technology centre of excellence.
Facilities include specialist development laboratories, clean rooms, test and characterisation equipment, a micropackaging prototype production line and additional micro-manufacturing sites, located at Rousset, Gardanne and Toulouse. Partners and local SMEs have access for development work and proof of concept or prototyping. The aim is to allow local firms to explore disruptive approaches in order to differentiate and ultimately develop viable and competitive technologies.
When it comes to design tools for 3d packaging, the general view is there is much to be done. Cadence's tools, for example, are said to support package design, including assembly rule checking, die stack editor and 3d visualisation. To come, are tools supporting embedded approaches for passives, mems and other devices, 'what if' analysis for changing the stacking order, and modelling for addressing power and temperature issues.
The company is also working with Apache Design Solutions to develop some common interfaces for their respective tools. For key customers, Cadence liaises between the foundry and third party packaging services.
Apache's Jérome Toublanc explained. "The challenge is developing model based solutions for the die environment, including packaging, and concurrent design. It is important to have tools that can import multidie full layout or model based die simulations."
System level thermal modelling issues are important for stacked die, as well as emc analysis and leakage estimation. Insight SiP uses Agilent tools, combining schematic capture and layout with rf and electromagnetic simulation. "A small and cost effective tool," Beghin remarked. "The major eda design tool vendors need to improve dramatically, particularly for thermal and emc analysis."
He agreed that Cadence has good place and route tools. "But that is not the critical issue. Ansoft and Agilent have the best rf and em simulation tools." But the eda sector will need to address design portability issues, Beghin believes.
For the future, Insight SiP is expecting new substrate materials, including fabrics, glass, plastic and organic materials. ST believes photonics on silicon will be essential to meet bandwidth demand and cloud computing applications.
Despite the new 3d packaging technologies and their rapid take up, the traditional challenges still remain: the provision of commercially viable, high volume assembly techniques; known good die; and maximising yield.
On the yield issue, ST's Jean-Luc Jafford commented: "You can't avoid defects. You have to deal with them."