Latest In Depth Technology News

Time is running out

Whilst the electronics industry may be in the early stages of discussion regarding the implications of WEEE and RoHS, time to comply is running out. By Vanessa Knivett.

A matter of protocol

Serial communications: system requirements and design challenges. By Nilam Ruparelia. By the late 1990s, as Moore’s Law continued to deliver semiconductor integration and processing power, high bandwidth chip connectivity had become a significant bottleneck. It quickly became clear that, if the industry did not figure out ways to increase data transfer rates among high performance logic chips (like cpus, wan framers, dsps and network processors), it would end up with many thousands of pins on each multimillion gate device. High speed serial communication surfaced as the obvious solution and cmos technology, at geometries of 0.18um and smaller, enabled integration of high speed plls and I/Os in standard logic chips. Unfortunately, the enthusiasm for high speed serial communication resulted in a plethora of confusing serial protocols. A large number of protocols addressed the ‘sweet spot of 1 to 3.2Gbit/s. To make matters worse, some six other protocols surfaced in the 2.5 to 3.2Gbit/s serial rate range. At first glance, it may seem an abundance of standards would mean a fragmented market, or that a lot of energy was being spent primarily on I/O, but most protocols cater to specific applications. It is useful to understand how system level requirements make one protocol more applicable than another for a particular application. Similarly, we can glean useful information from board design challenges related to signal integrity issues, helping to prepare us for next generation protocols and system designs at 5 to 10Gbit/s.

Disk drivers

How are manufacturers responding to the need for high capacity recordable dvds? By Vanessa Knivett.

Through the eye of a needle

Logic devices get smaller and smaller. By Graham Pitcher. Engineers can probably agree on one thing: designs don’t always go quite as planned. And, when they don’t, there are decisions to be taken. Do you, for example, redesign a more expensive programmable part or a complex pcb and take the risk of being later to market than you intended? Or do you take the shorter route; correcting the errors using discrete logic devices? Logic devices address a problem frequently encountered in pcb design: the need for ultra small sized circuits in an already crowded layout. With innovative packaging options, the parts need only a fraction of the mounting area required for a conventional small outline package. Difficulties arising from wiring density, impedance – or the worst case of costly redesign – can often be overcome by strategic use of discrete logic. According to Fairchild (, its TinyLogic range gives engineers the ability to implement design changes without having to redesign silicon or change pcb layouts. The range has been developed with space constrained products in mind – and consumer electronics in particular. Single and dual gate logic functions are available and these can be placed where they are needed to simplify routing, minimise propagation delay and noise. Fairchild’s Ultra Low Power (ULP) series is designed for applications where battery life is critical. This product is designed for ultra low power consumption within the Vcc operating range of 0.9 to 3.6V. The internal circuit is composed of a minimum of inverter and buffer stages to enable ultra low static and dynamic power. The Ultra Low Power A (ULP-A) series is targeted at applications that require high speed, high drive and low power. This product is also designed for operation with Vcc ranging from 0.9 to 3.6V.

Now you see it …

After a long break, we revive the Test Bench series of articles with a look at a configurable logic device with a difference. By Philip Ling.

Standards dance

SoC standards abound from various organisations, but they seem to be dancing to the same tune after all. By Louise Joselyn

Hold that pose!

Increases in storage density mean we may soon be able to capture every waking moment. By Philip Ling.

Time waits for no man

With engineers now having to cope with multiple signals at very fast signal rates, how is test hardware meeting their needs? By Vanessa Knivett.

The eyes have it

High speed serial communications links need to be designed and tested carefully. By Graham Pitcher. It wasn’t long ago that data communications was a relatively simple design task. Today, all that has changed. To meet the demand for higher and higher data rates, designers are moving to serial data links. Along the way, they are having to deal with some fundamental physical issues. Yves Braem is a signal integrity engineer with Tyco Electronics’ circuit and design department ( He said: “With higher data rates, the problems you encounter become more and more significant. As frequency increases, transition times get smaller and the electrical waveform ‘sees’ the transmission path in ever more detail. This means you have to design carefully.” In Braem’s opinion, high speed data links bring an increasing number of signal integrity problems as data rates move beyond 2.5Gbit/s. “Designers not only have to select reliable and first class components and interconnections, they also have to consider the interfaces between the different ‘building blocks’ in the system.” In his view, these interfaces used to be electrically short because the signal wavelength was much bigger than the component itself. “Now,” he continued, “the interface itself can jeopardise the whole interconnection quality.” He believes three aspects need to be considered when designing high speed backplanes: pcb traces; connector/board interfaces; and board to board connectors. “The throughput of signal traces in pcbs is limited by trace losses, consisting of skin effect and dielectric losses,” he noted. These losses combine to limit the total trace length in the system and, therefore, system size. Dielectric loss can be reduced by specifying low loss pcb materials, whilst skin effect losses are reduced through the use of wider traces. But designers may not be able to specify wider because of space constraints and other factors.

Right by design?

The ubiquity of Ethernet masks the complexity beneath it, as network traffic reaches data rates of 10Gb. By Philip Ling.

Subscribe to our Newsletter

Most popular

Deep fools

In not much more than a decade, deep learning has moved from a research curiosity to ...