23 November 2010

Universal DDR Controllers for embedded DRAM interfaces

Synopsys has announced the DesignWare Universal DDR Protocol and Memory Controllers, which it says offers improved performance and reduced cost of embedded DRAM interfaces.

Both controllers are said to support the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards, deliver memory system performance of up to 2133 Mbps, and offer a broadly utilised DFI 2.1 compliant interface to the DDR PHY.

According to Synopsys, the memory controller helps reduce both the latency and silicon area by up to 50% compared to Synopsys' previous generations of DDR memory controllers, improving the DRAM interface performance and reducing overall chip costs. It has been designed to provide efficient DDR control and protocol translation for applications, without the need for a multi ported memory controller.

The controllers are said to enable designers to easily integrate multiple DDR interfaces into one design with less risk and improved time to market. The DDR Memory Controller reportedly accepts memory access requests from up to 32 application side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock.

Author
Laura Hopperton

Supporting Information

Websites
http://www.synopsys.com/ddr

Companies
Synopsys Inc

This material is protected by Findlay Media copyright
See Terms and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the sales team.

Do you have any comments about this article?


Add your comments

Name
 
Email
 
Comments
 

Your comments/feedback may be edited prior to publishing. Not all entries will be published.
Please view our Terms and Conditions before leaving a comment.

Related Articles

Memory boom drives semi sales

Memory chips were the star performers of 2013, reports IHS, enabling the global ...

Toshiba starts 15nm flash

Toshiba is to commence 15nm NAND flash production at the end of the month at ...

SRAM consumes 50% less power

Early tests of SureCore's low power SRAM design are said to confirm the results ...

Boosting processing power

Micron Technology appeared at the 2013 Supercomputing conference, where it ...

Avoid counterfeit electronics

It's been discussed and analysed for years, yet there does not seem to be an ...

Leaving a legacy

What happens to a process technology when it falls behind the leading edge?

Test and repair solution

Many large SoC designs today incorporate several third party IP cores that ...

Transferring Data in Non-Networked ...

Nexus (GB), the UK partner of portable data token manufacturer Datakey ...

Xilinx generic flash memory interface ...

This white paper shows how a generic flash memory interface can be combined ...

EEPROM device for DDR4

Microchip is now shipping a 4Kb I2C serial presence detect EEPROM device, ...

Processors part with ECC

Toshiba Electronics has expanded its range of 24nm BENAND single level cell ...

Serial EEPROM devices

Microchip's new family of serial EEPROM devices come with a unique, ...

DDR memory termination

In the third video of our Power Solution series, product marketing engineer for ...

Android 2.3 embedded designs

Have questions about using Gingerbread for your embedded design? This video ...

PCM puzzle swap demo

This demo will show how PCM's overwrite capability can optimize your subsystem, ...

Flash drives semi technologies

Demand for NAND flash is said to be growing at 45% per year, driven mainly by ...

Flash storage vs. disk drives

The question on everybody's lips within the computer memory industry is whether ...

Claire Jeffreys, NEW

Claire Jeffreys, events director, National Electronics Week, talks with Chris ...

Matthew Trowbridge, Renesas

Matthew Trowbridge, Renesas Technology Europe's ceo speaks with Graham Pitcher

Moshe Gavrielov, ceo, Xilinx

Moshe Gavrielov, Xilinx' president and ceo speaks with New Electronics