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Xilinx, Micron platform enables higher data rates for 40/100G networking systems


Xilinx and Micron Technology have announced the first public hardware demonstration of an fpga interfacing with RLDRAM 3 - a new memory standard for high end networking applications such as packet buffering and inspection, linked lists and lookup tables.

Operating with Virtex-7 and Kintex-7 fpgas at data rates up to 1600Mb/s, Micron's RLDRAM 3 memory is designed to combine high density, high bandwidth and fast sram like random access. This, says Micron, enables a 60% higher data rate and memory bandwidth compared to the previous generation. It also enables 40 and 100G networking systems that require higher speed, higher density, lower power and lower latency.

Virtex-7 and Kintex-7 fpgas are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3. According to Xilinx, this provides a significant boost to system performance for high performance wireless and wired networking systems.

Micron states that RLDRAM 3 memory uses an innovative circuit design to minimise the time between the beginning of an access cycle and the instant the first data is available. Ultra low bus turnaround time is designed to enable higher sustainable bandwidth with near term balanced read to write ratios.

"The new RLDRAM 3 interface is ideal for Xilinx and Micron's mutual customers in the high end networking space who require higher speed, higher density, lower power and lower latency," said Derek Curd, technical marketing manager at Xilinx. "The RLDRAM 3 hardware demonstration shows how we're able to achieve a much more efficient transfer of network data."

Robert Feurle, vice president of Micron's DRAM marketing, added: "Xilinx has been a long time partner of Micron, going back to the early definition efforts of RLDRAM 3 memory. Together, we welcome the ability to demonstrate and deliver performance advantages of RLDRAM 3 with the latest Virtex-7 and Kintex-7 families."

Hardware demonstrations are available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012.

Author
Chris Shaw

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