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Vitesse and AppliedMicro collaborate on 40/100G eFEC technology

Vitesse, AppliedMicro collaborate on 40/100G eFEC technology

Vitesse Semiconductor and Applied Micro Circuits have announced the industry's first collaboration to drive a standard approach for 40G and 100G enhanced forward error correction (eFEC) technology.

Forward error correction is widely used in fibre optic communications to reduce bit error rate in typically noisy signal environments. As metro and long haul networks transition from 10G to 40G, and up to 100G high speed data rates, the collaboration has been established to address the increasing challenges in developing cost effective, improved signal to noise ratio solutions.

AppliedMicro will license Vitesse's patented portfolio of 40G and 100G hard decision eFEC cores for its fpga and assp solutions. These are aimed at emerging optical transport network (otn) applications requiring net electrical coding gain (necg) with the lowest implementation complexity and cost. The two companies will mutually cross license three otn applications including AppliedMicro's 10GE LAN Signal Mapping to OTU2 Signal patent and Vitesse's Continuously Interleaved Error Correction patent.

"Providing the industry a standardised eFEC approach for emerging otn solutions in metro and long haul networks is our ultimate goal," said Steve Perna, vice president of product marketing at Vitesse. "This effort provides significant technology advancements and value to customers who need an effective and reliable way to transmit data, voice, and video at faster rates in otn applications. As networks migrate and Ethernet becomes the ubiquitous protocol, this capability will be increasingly critical."

Chris Shaw

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