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UltraSOC develops RISC-V processor trace

Rupert Baines, CEO, UltraSOC

A processor trace developed by UltraSOC will be offered for adoption by the RISC-V Foundation as part of the open source specification. Processor trace functionality allows a program’s behaviour to be viewed in detail, instruction-by-instruction.

According to the company, five core vendors have announced support for the specification, said to be a key function for software developers and an important step in the development of the RISC-V ecosystem.

“RISC-V is a great architecture: but an architecture is not enough,” said Rupert Baines, pictured, UltraSoC’s CEO. “Customers need the whole ecosystem [and] UltraSoC is aiming to play a major role in that with debugging and development IP – and processor trace for RISC-V is a significant supporting pillar in that effort.”

UltraSoC, which is working with Andes, Codasip, Roa Logic, SiFive and Syntacore, plans to submit a proposed processor trace format to the RISC-V Foundation later in 2017.

Graham Pitcher

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