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TSMC takes on Intel after claims about transistor density

TSMC's recently appointed co ceo and president Dr Mark Liu used the company's latest financial results meeting to take exception to Intel claiming technology leadership.

Accusing Intel of being 'misleading', Dr Liu said: "We usually do not comment on other companies' technology. To me, it's erroneous and based on outdated data."

Intel used the graph shown here in a presentation made in November 2013 to investors. The graph plots chip area on a log scale on the vertical axis against Intel's and TSMC's relative achievements at four technology nodes; 32/28nm (Intel/TSMC), 22/20nm (Intel/TSMC), 14/16nm FinFET (Intel/TSMC) and 10nm. Intel claimed the data was compiled from a TSMC keynote, a presentation at the 2010 ARM TechCon and its internal assessments.

"The plot shows TSMC is ahead on area scaling at 32/28 and 22/20," said Dr Liu, "but at 16nm, the data shows a little bit of an uptick, then follows the same slope to 10nm."

In fact, Dr Liu claims TSMC has the better performance. "We took the approach of using the FinFET transistor to improve the performance on top of the similar back end technology in our 20nm process. This transistor performance, and innovative layout methodology, can improve the chip size by about 15%. Because transistor drive is much stronger, you don't need such a big area to deliver the same driving circuitry."

TSMC chairman Morris Chang noted: "We live on technology, just as Intel thinks or says it does. It's extremely important that our 16FinFET process provides good enough technology, so the Grand Alliance [TSMC's customers, EDA and IP partners and key equipment and materials suppliers] can outcompete Intel and Samsung. And we feel fairly confident that we'll do that."

Meanwhile, Dr CC Wei, TSMC's other president and co ceo, pointed to the availability of the 20SoC process. "It's a technology that we developed to enable our customers to lead in the mobile device market," he said. "We are in volume production right now."

Dr Wei said: "I'm very confident that 20SoC is the highest gate density process in volume production at 20nm. I don't see any company today that can claim this kind of production and this kind of gate density. Most of our competitors are not even in the game yet."

Dr Wei also pointed to a tripling in demand for 28nm production in 2013 and believes this will grow by another 20% this year. "All the increase is coming from 28HPM." The latter is TSMC's high K metal gate process.

28 HPM is said to bring a 30% speed boost over 28LP for the same power consumption. Alternatively, process will reduce power consumption by 15% at the same clock rate. Dr Wei expects 'more than 100 tape outs from about 60 customers' using 28HPM in 2014, as well as growing interest in 28HPC, a low cost version of 28HPM.

TSMC reported revenues of around $20.1billion in 2013. More than half of this (54%) came from communications devices – an increase of 29% over 2012 – and 34% of revenue came from 28nm devices.

Chang noted: "For full year 2014, we forecast the worldwide semiconductor industry will grow by 5%. For the fabless industry, we forecast 8% growth and for the foundry industry, we forecast 10% growth. For TSMC, we are forecasting revenue growth surpassing that of the foundry industry. Our 2014 capital budget is estimated to be between $9.5bn and $10bn, similar to that of last year." He added that about 95% of this expenditure is for advanced technologies.

Asked about progress towards extreme ultraviolet lithography, Dr Liu said TSMC is not currently planning to use it at the 10nm node. "However, we have been working closely with ASML and have set a target for throughput." He added that if ASML can reach this target, EUV could be used at the 10nm node for 'cost reduction'.

Author
Graham Pitcher

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