22 July 2009
TSMC supports 28nm chip design and system in package
TSMC has unveiled the latest version of its design methodology, allowing designers to address the 28nm node.
Reference Flow 10.0, a key component of TSMC's Open Innovation Platform, not only improves design margins and increases yields, but also addresses the design challenges posed by 28nm process technology and supports system in package (SiP) design.
According to the company, the Open Innovation Platform paves the way for eda tools to be ready for 28nm. New to the flow is an RTL-to-GDSII chip implementation track from Mentor Graphics, in support of customers' EDA usage. Reference Flow 10.0 further enables existing ecosystem partners Altos, Anova, Apache, Azuro, Cadence, CLK DA, Extreme DA, Magma, Nannor, and Synopsys to bring EDA innovations to customers through collaboration with TSMC.
While the previous nine generations of Reference Flow have focused on SoCs, Reference Flow 10.0 introduces SiP design solutions, including SiP package design, electrical analysis of package extraction, timing, signal integrity, IR drop and thermal to physical verification.
Author
Graham Pitcher
Supporting Information
Websites
http://www.tsmc.com
Companies
TSMC Europe BV
This material is protected by Findlay Media copyright
See Terms
and Conditions.
One-off usage is permitted but bulk copying is not.
For multiple copies contact the
sales team.