18 June 2009
TSMC extends SiON/polysilicon to 28nm node
TSMC has extended the use of silicon oxynitride (SiON)/polysilicon to the 28nm process node using a dual/triple gate oxide process.
Other characteristics of this technology – presented in a paper at the 2009 Symposia on VLSI Technology and Circuits in Kyoto – include high density and low Vcc_min 6T sram cells, low leakage transistors, conventional analogue/rf/electrical fuse components and low RC Cu/low K interconnect.
"This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology," said Dr Jack Sun, TSMC's vp of R&D. "We continue this quest to support the most advanced applications being designed by the innovators in the semiconductor industry," he said.
Additionally, the paper reports good functional yields of a 64Mbit sram with a cell size of 0.127µm² and a raw gate density of up to 3900kgate/mm². TSMC says the performance of these test devices 'proves the manufacturability of this technology'.
According to TSMC, the development demonstrates its commitment and ability to extend SiON/poly as a cost effective solution for low power and high performance devices. The paper describes low standby and low operating power transistors using SiON optimised with strain engineering and aggressive oxide thickness provide a speed improvement up to 40% or reduction in active power consumption of 30 to 50%, compared with a 45nm process.
TSMC plans to deliver its 28nm process in early 2010 as a full node technology offering options of power efficient, high performance and lower power technologies.
Author
Graham Pitcher
Supporting Information
Websites
http://www.tsmc.com
Companies
TSMC Europe BV
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