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New technology boosts STA runtime and capacity by up to 10 times claims Synopsys

system on chip

Synopsys has launched PrimeTime HyperScale technology, which it says enables static timing analysis (STA) to scale beyond 500million instances. According to Synopsys, the technology makes it possible for designers of large SoCs to see block level timing in relation to the full chip and boosts static timing analysis runtime and capacity by five to 10 times.

The PrimeTime HyperScale technology has been designed for large SoC physical implementation flows where designs are implemented in blocks and then assembled at the chip level for final timing closure and signoff.

Synopsys claims it improves the timing closure process by providing a 'better mechanism' to look at block level timing in the context of the full chip timing earlier in the design process. By directly reusing block level timing analysis and constraints, it is said to enable a five to 10 times boost in full chip STA runtime and capacity without the accuracy limitations in current modeling techniques.

Its auto generation capabilities are designed to provide accurate and up-to-date timing contexts for the chip and block throughout the design process.

"As SoCs continue to increase exponentially in complexity, scalability of the design flow is a crucial factor in maintaining productivity," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "By adding HyperScale technology, the … release of PrimeTime includes a significant innovation to extend STA scalability for the next five to 10 years. This release represents an important milestone in delivering higher design team productivity both today and in the future."

Author
Chris Shaw

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