18 May 2009
Structured messages ease SystemVerilog testbench debug
In the latest release of its Verdi automated debug system, eda specialist SpringSoft has it is providing 'comprehensive SystemVerilog Testbench (SVTB) debug support'.
Fully integrated with the company's Novas family of verification enhancement products, the latest release of Verdi is said to feature a new structured message based method for automating SVTB debug.
Along with an automated message based logging mechanism and additional testbench specific comprehension tools, the system also feature an interactive simulation mode that can be used to pinpoint issues not uncovered via logging.
Scott Sandler, vp of worldwide corporate marketing, pictured, said: "Engineers have been using archaic methods, including print statements, so we are looking to make debug easier using the structured message approach." Sandler noted this allows designers to 'instrument' code by inserting messages, rather than print statements. "When they are debugging," he continued, "they see a waveform and they see messages – and these messages can be loaded with information. It's an aid to comprehension because if you don't have a structured method, you end up single stepping, which can be tedious when the software has a million lines."
Author
Graham Pitcher
Supporting Information
Websites
http://www.springsoft.com
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