01 June 2012

ST tapes out 20nm test chip using Cadence design tools

Cadence has announced that it has helped STMicroelectronics tape out a 20nm test chip which incorporates analogue and digital methodologies to enable mixed signal SoC design.

The companies said they collaborated using the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff in addition to the development of a foundational IP and SKILL based process design kit (PDK) for the 20nm process.

"At 20nm, custom analogue IP creation and digital implementation are highly interdependent, and an optimal methodology must cover the custom analogue and digital aspects of mixed signal chip design, verification and implementation," said Dr Chi-Ping Hsu of the silicon realisation group at Cadence. "Working together over the past two years, Cadence and STMicroelectronics successfully deployed an efficient methodology and design automation to address the requirements for designing complex mixed signal SoCs."

ST performed automated layout generation using the Cadence Virtuoso Layout Suite in its custom IP design development, including foundation IP, PLL and video DAC. To help ensure accurate results, designers used a 20nm PDK that enabled advanced capabilities such as Modgens, constraints and space based routing. The Encounter Digital Implementation system provided 20nm physical implementation capabilities for the tapeout, handling 20nm process requirements during placement and optimisation as well as routing.

"We selected Cadence at the start of our 20nm development and today's milestone demonstrates the success of that collaboration," said Philippe Magarshack, group vice president of technology research and development at STMicroelectronics.

Simon Fogg

Supporting Information


Cadence Design Systems (UK)Ltd
STMicroelectronics NV

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