15 May 2012
Cadence upgrades verification software
Cadence Design Systems has unveiled a new in circuit acceleration approach for its System Development Suite. Based on its Incisive and Palladium XP platforms and featuring extensions to the Verification IP (VIP) Catalog, the upgrades are said to give engineers the ability to speed the verification of large scale SoCs, subsystems and systems.
Franck Schirrmeister, director of product marketing for Cadence's System and Software Realisation Group, said: "Customers need new approaches, not only for SoCs, but also for system verification; making sure the design works in its environment." He noted the upgrades represent a 'significant improvement' to the System Development Suite. "We're offering a new capability called In Circuit Acceleration, which is a blend between in circuit emulation and simulation acceleration."
The move, which builds on last year's launch of the System Development Suite, has been made to help reduce the cost and time issues associated with simulation and emulation. "Incisive and Palladium are connected," said Schirrmeister. "Traditional rapid prototyping has been hard to set up; sometime, it takes a couple of months. By using the same front end, we've brought the set up time down to weeks."
For the future, Schirrmeister said the vision is to move from a set of connected platforms to 'one big system' by getting Incisive and Palladium even closer together. "We're not there yet, but we have made significant strides."
Meanwhile, the VIP Catalog has been upgraded with the addition of the Denali API. Denali was acquired by Cadence in 2011. Susan Peterson, product marketing director, said: "It's a catalogue of IP for more than 40 interface protocols, with more than 6000 models from 85 manufacturers. We have many customers who want to get into system level verification and, when that happens, simulation runs out of steam."
Accelerated VIP, which is compatible with the Universal Verification Model, enables users to move from simulation to acceleration, in circuit acceleration and in circuit emulation, allowing them to verify complex systems and SoCs that are too large for traditional rtl simulation.