10 May 2010
Cadence moves to speed SoC design, cut costs
Cadence has developed a platform approach that, it claims, reduces SoC development costs significantly, while improving quality and accelerating production schedules.
Called the Open Integration Platform, the approach comprises integration optimised IP from Cadence and its partners, an Integration Design Environment; and on demand integration services. Cadence mixed signal design, verification and implementation products and solutions are the underpinning of the Open Integration Platform.
The justification, says Cadence, is the huge increase in SoC development costs, with IP related costs accounting for up to 25% of the hardware design spend. The Open Integration Platform has been developed to help to reduce those costs by focusing on an application driven development process and by encouraging open, standards based collaboration.
Vishal Kapoor (pictured), Cadence's vp of product management, noted: "Qualification is beginning to represent a significant part of SoC development cost. When companies get IP, they're not sure of its quality, so push to the verification level, which adds cost."
The Integration Design Environment is a suite of products based on existing technologies that enable developers to create, evaluate, acquire and integrate IP. Kapoor noted: "It's a set of tools which starts from the chip planning level. It's targeted at integration, while supporting the creation of IP, hardware and software."
Initial partners in the Open Integration Platform include GDA, IBM, RapidBridge and Sonics. "This is the first step in the Open Integration Platform and there will be more developments later this year," Kapoor added. "There will be more partners and a broader IP portfolio."
* Meanwhile, Cadence has also launched a high performance verification computing platform called Palladium XP. The system supports designs with up to 2billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system level solutions, including low power analysis and metric driven verification.