28 March 2011
Smart power semiconductor technology reduces power consumption
STMicroelectronics claims the next generation variation of its smart power technology could enable significant reductions in the power consumption of a range of electronic systems.
The company has produced a demonstrator chip with a medical equipment supplier for ultrasound scanners. Current technology typically handles eight channels, but according to ST the new semiconductor technology can handle more than 100 channels. Potential applications include new medical equipment and battery chargers in hybrid electric vehicles.
The new technology is a variation of ST's Bipolar cmos-dmos (BCD) smart power semiconductor technology that combines silicon on insulator (SOI) substrate technology with 0.16µ lithography. According to ST, this will enable chip designers to combine high density logic circuitry (1.8 and 3.3V cmos) with full dielectric isolation and a component portfolio including power mosfet transistors that can operate up to 300V, low noise devices, and high value resistors, leading to asics that cannot be implemented using conventional bulk silicon substrates.
"Semiconductor technologies that can drastically reduce electrical energy consumption in consumer and industrial appliances have existed in the labs for many years and their potential contribution to the reduction of worldwide power consumption is significant," said Claudio Diazzi, group vice president, Technology R&D, STMicroelectronics. "However, the cost of these technologies has previously been too high to make them commercially viable. We believe that this new smart power technology will make a significant difference." The development of the technology is part of an advanced European R&D project.
Author
Chris Shaw
Supporting Information
Websites
http://www.eniac.eu
http://www.smartpm.eu
http://www.st.com
Companies
STMicroelectronics NV
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