12 July 2011
Samsung, ARM tape out 20nm test chip
Samsung's foundry business has successfully taped out a test chip based on its 20nm process with High-k Metal Gate technology.
The company says it is taking steps to validate the design infrastructure for its latest manufacturing technology node. Samsung Foundry's 20nm early access process design kit is currently available to customers who are in the initial stages of designing their next generation products.
"This is a significant milestone with regards to the design ecosystem that needs to be developed in parallel with the manufacturing process," said Dr Kyu Myung Choi, vp, device solutions, Samsung Electronics. "The design methodology, tools and IPs used on this 20nm test chip bring together the most advanced technology from our design infrastructure partners together with Samsung process and design technology to solve critical design challenges so our customers can deliver their latest chips to market quickly and efficiently."
According to Dr Choi, many new 20nm design kits, router and other design enablement features were used in this first test chip to support novel process innovations. These included new device structures, local interconnects and advanced routing rules. The company worked with its ecosystem partners ARM, Cadence and Synopsys to develop the chip.
ARM physical IP and processor IP were used to build a prototype SoC test chip. Samsung also utilised both the Cadence unified digital design flow and the Synopsys Galaxy Implementation Platform to implement different components of the test chip in order to validate its design methodology for both Cadence and Synopsys design flows.
Cadence Design Systems (UK)Ltd
Samsung Electronics (UK) Ltd
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