10 March 2011
Real time design rule checks available for custom chip designers
In a move that brings instantaneous design rule checking to those designing chips at the leading edge, Mentor Graphics has launched Calibre RealTime platform. The first release provides instantaneous design rule checking (DRC) in the SpringSoft Laker custom ic design and layout solution, using the same Calibre decks as the signoff flow.
The move is said to improve design speed and quality of results by giving designers access to Calibre's signoff engines and qualified decks during design. This, it claims, allows designers to optimise their layouts for performance without sacrificing manufacturing yield.
Joseph Davis, product manager, said: "There has been an 80% increase in the number of rules and their complexity, dealing with stress and lithography aspects. These issues control chip performance." Davis added this was particularly important at the transistor level, where work is done by hand to get the best performance from analogue and mixed signal designs. "You're talking about 1000 checks for transistors and about 3000 checks overall," he pointed out. "All of this means more design iterations."
Mentor launched InRoute last year as a means of bringing sign off into design creation. Calibre RealTime is said to bring this to the custom design environment.
Davis claims real time checking can be a major time saver. Citing a 90nm design with 1100 checks and 5900 shapes, Davis said previous tools would take 10 to 20s per check. Calibre RealTime, however, can do each check in 0.2s. "If you're running checks say 200 times a day, you are looking at man weeks of run time. Calibre RealTime changes the game; it puts time back in the designer's pocket, allowing them to further optimise their design."
Mike Buhler, marketing director, added: "People say advanced nodes are hard. We're saying if you have the right tools, you can take advantage of advanced nodes."
Mentor Graphics (UK) Ltd
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