26 September 2014
Platform to speed design bring up and time to market for SoCs
In a move designed to enable earlier software bring up and shorter time to market for SoCs, Synopsys has launched Verification Continuum, a software platform which provides virtual prototyping, static and formal verification, simulation, emulation, FPGA based prototyping and debug in a unified environment.
"Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry," claimed Manoj Gandhi, pictured, general manager of Synopsys' Verification Group. "The significant verification R&D investments Synopsys has made over the past two years are already showing promising early results towards helping customers reduce time to market by months for advanced SoC designs."
Verification Continuum brings together Virtualizer virtual prototyping, Verification Compiler static and formal technologies, VCS simulation, ZeBu emulation, HAPS FPGA based prototyping and Verdi3 debug.
It also features Unified Compile, based on the VCS simulator front end. This is said to provide a simulation like interface across the verification flow, allowing engineers to transition between the various tools in the platform as required by the verification task. Synopsys contrasts this with existing point tool based flows, which it says require extensive set up, as well as effort to move a design between the different tools.
Verification Continuum also features FPGA based emulation and prototyping, helping to speed bring up time compared with earlier approaches.