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Parallel approach

Reconfigurable processing at EPF.

The first example of Motorola's reconfigurable processing technology was presented at the Embedded Processor Forum (EPF). It joins the ranks of Elixent and PicoChip – both UK companies who also presented papers at the forum on their reconfigurable technologies.

The move goes some way to justifying the relatively new approach, swelling the category of devices based on massively parallel processing arrays – seen by some as the only way of meeting the growing demand for more dsp power in applications such as 3G basestations.

But instead of being a potential threat to the dsp, Motorola's technology has been designed to operate alongside it as a complementary device. Based on technology licensed from Morpho Technologies, the MRC6011 comprises six cores, each with 16 reconfigurable compute elements, giving a total of 96 compute elements on one device. Each of the six cores has its own risc processor, dma controller and frame buffer.

An integrated development environment has also been developed to support code development using the MRC6011 and its associated dsp, the recently introduced MSC8102.

Author
Graham Pitcher

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