13 March 2013
Nano transistor enables 3d stacking
As transistors get smaller, gate control over the channel becomes less effective and leakage begins to interfere with the transistor's operation.
Looking to overcome this problem, a team of researchers at the Laboratoire d'Analyse et d'Architecture des Systèmes and Institut d'Électronique, de Microélectronique et de Nanotechnologie (LAAS and IEMN) has built what is said to be the first truly 3d nanometric transistor.
The device consists of a tight vertical nanowire array of about 200nm in length linking two conductive surfaces. Each nanowire is surrounded by a chromium gate, which controls current flow. The team says this provides optimum transistor control for a system of this size. While the gate is only 14nm long, its capacity to control the current in the transistor's channel is said to meet the requirements of modern microelectronic devices.
The team says the architecture could lead to the development of microprocessors in which the transistors are stacked. The number of transistors in a given space could thus be increased, along with the performance of microprocessors and memory units.
Another advantage claimed for these components is that they are relatively simple to manufacture and do not require high resolution lithography. In addition, 3d transistors could be integrated into conventional microelectronic devices.
The researchers now plan to continue their efforts to reduce the size of the gate to less than 10nm and the team is now looking for industrial partners.
Author
Graham Pitcher
Supporting Information
Websites
http://www.cnrs-dir.fr
http://www.laas.fr
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