03 August 2012
LabVIEW add on accelerates system design through increased abstraction
Looking to simplify fpga algorithm design, National Instruments has unveiled the LabVIEW FPGA IP Builder add on which uses Xilinx Vivado high level synthesis technology.
The add on is designed to enhance productivity by reducing the need for manual optimisation of high performance algorithms. Instead, users specify functional behaviour along with design constraints and the software automatically generates a hardware implementation.
"Our vision for the LabVIEW platform is to empower domain experts to represent their algorithms using natural programming paradigms and provide a seamless path for deploying to high-performance hardware," said David Fuller, vp of applications and embedded software at NI. "High level synthesis technology is central to this vision – it empowers system designers to spend less time optimising their FPGA algorithms and more time innovating."
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