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IP means image processing

The annual semiconductor IP event in Grenoble, attracted top flight speakers and a record number of delegates. Louise Joselyn reports from Grenoble.

Heterogeneous multicore design and programmable, reconfigurable processors are being touted as the solutions for delivering the computation needed for media processing functions on portable products, while keeping power requirements within sensible bounds. Graphics and image processing, demanding heavy duty computations and clock frequencies of 200MHz and beyond, and the quest for energy efficiency are driving a change in SoC design approach. “Data and function parallelism have to be exploited,” declared Gagan Gupta of ARC. “This should be combined with energy aware design processes,” he added.
Haydn Povey of ARM added that a heterogeneous multicore approach enables the integration of new features for energy efficiency, such as only powering components when they are needed. Jeroen Leijten of Silicon Hive remarked that HD applications will need to exploit parallelism beyond established limits, covering memory and I/O, as well as processing.
Leitjen emphasised the importance of designing for power efficiency, not just in terms of power saving when functions are idle, but for reducing power consumption in operation too. Various techniques exist for optimising pre and post video processing functions, for example.
Gupta recommended a holistic approach focused on optimising tasks and processor cores individually. For example, accelerating a specific compute intensive decoding or motion estimation task, can result in significant overall power saving. Of course, reprogrammable and reconfigurable processor cores (available from ARC and others) open up a world of options. Other tips for memory architectures include storing data in block form, not crossing row boundaries, and not spanning cache lines, to reduce the number of memory accesses. Some advocate avoiding cache altogether.

Louise Joselyn

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