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IAR Systems updates RISC-V development tools

IAR Systems, a supplier of software tools and services for embedded development, has announced a new version of the toolchain IAR Embedded Workbench for RISC-V.

Version 1.11 adds support for custom extensions as well as further enhanced optimisations for code execution speed.

One of the major benefits of using RISC-V is the flexibility the architecture provides, which enables OEMs as well as SoC vendors to design custom cores with the exact definitions needed for the application or product. By adding support for custom extensions, IAR Systems is looking to make it possible for these companies to make full use of the capabilities of the leading embedded development toolchain for developing applications based on custom cores.

Through the use of optimisation technology, IAR Embedded Workbench helps developers ensure the application fits the required needs and optimise the utilisation of on-board memory. This also enables companies to aggregate value by adding functionality to an existing platform.

Version 1.11 of IAR Embedded Workbench for RISC-V adds additional tweaks for code speed, resulting in significantly higher performance of the generated code.

To ensure code quality, the toolchain includes C-STAT for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, and also detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.

“By using IAR Embedded Workbench for developing software for custom RISC-V cores, designers gain full flexibility for innovation and differentiation without compromising code quality or performance,” said Anders Holmberg, Chief Strategy Officer, IAR Systems. “Our current users of the toolchain report major performance improvements compared to other RISC-V tools. OEMs that are exploring using a RISC-V core for their next embedded project can feel confident that we are delivering best in class optimisations for size and speed, as well as the support they need to keep project deadlines,” he concluded.

RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles. In May 2019, IAR Systems released the first version of IAR Embedded Workbench for RISC-V.

Author
Neil Tyler

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