02 March 2012
MathWorks enhances range with fpga and asic coding and verification products
HDL coder improves the fpga/asic design flow
In a move described as a 'significant enhancement' to its product range, MathWorks has launched HDL Coder, which allows HDL code to be generated directly from MATLAB and used to implement fpgas and asics.
HDL Coder generates portable, synthesisable Vhdl and Verilog code from MATLAB functions and Simulink models. As a result, engineering teams can identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high integrity applications.
Graham Reith, senior applications engineer with MathWorks, said: "It's a big step forward. A lot of designs start off in Matlab and end up in an fpga or asic." He added that it wasn't only about code generation. "It's also about workflow. When people write code in MATLAB, they don't always think about the best implementation. This will help them to describe their algorithms."
Meanwhile, MathWorks has also announced HDL Verifier, which offers hardware in the loop testing capabilities for fpga and asic designs. According to the company, these two products will provide HDL code generation and verification across MATLAB and Simulink.
HDL Verifier supports 15 boards from Altera and Xilinx, providing interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, says the company, engineers can verify that their HDL implementation matches their MATLAB algorithms and Simulink system specifications.
Reith noted: "Engineers can take large designs and stream data back to MATLAB, building confidence that the design is working."