30 November 2009
Grid computing tackles statistical variability
Scientists at the University of Glasgow, in collaboration with colleagues from Edinburgh, Manchester, Southampton and York, have developed technology which will help in the design of future ics.
As part NanoCMOS, a £5.3million eScience project funded by the Engineering and Physical Sciences Research Council (EPSRC), the researchers have developed simulation tools which take advantage of grid computing to predict how billions of nanotransistors, each with their own atomic scale variations, will perform within a circuit.
Professor Asen Asenov, pictured, principal NanoCMOS investigator, said: "If we are to continue to shrink the size of transistors in order to develop ever more powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the statistical variability.
"Until now, Moore's Law … has been the driving force of the chip manufacturing and design industry, but the days of 'happy scaling' are over."
The simulations will help tackle the problem of 'statistical variability' within transistors, a major obstacle in the continued scaling of cmos process technology.
Statistical variations between transistors mainly occur due to the random number and position of discrete dopants. This statistical variability means that circuits may not perform as well as expected, despite being manufactured in an identical way.
However, Prof Asenov and his team have applied grid computing technology to tackle the problem in the framework of NanoCMOS, funded by the EPSRC, in collaboration with leading design houses, chip manufacturers and software vendors.
Using this approach, simulations of huge numbers of microscopically different nano transistors have been carried out on thousands of microprocessors on networked computer clusters consuming more than 20 years' of cpu time. As a result, the team has been able to predict for the first time, using 3d numerical simulations, how billions of microscopically different transistors will perform in future computer chips.
The simulations provide the scientists with information on the statistical distribution of the transistors' characteristics, helping to predict how many of the transistors in a chip will work.
Prof Asenov added: "The NanoCMOS project … will be a great benefit, not only to the major semiconductor manufacturers around the world, but also to the vibrant UK chip design industry."
Author
Graham Pitcher
Supporting Information
Websites
http://www.elec.gla.ac.uk
http://www.epsrc.ac.uk
http://www.nanocmos.ac.uk
Companies
EPSRC
University of Glasgow
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