23 February 2009
FPGAs for cost sensitive applications
Looking to meet the needs of cost sensitive, mid performance applications, Lattice Semiconductor has the LatticeECP3 family.
Produced on Fujitsu’s 65nm process, the range is said to offers the lowest power consumption and price of any serdes capable fpga.
Members of the family offer multiprotocol 3.2Gbit/s serdes with XAUI jitter compliance, DDR3 memory interfaces, dsp capabilities, high density on chip memory and up to 149,000 look up tables (LUTs).
“The LatticeECP3 family redefines mid range value based fpgas, not only by reducing costs, but also by reducing static power consumption by 80% and total power consumption by more than 50% for typical designs,” said Sean Riley, Lattice corporate vice president.
There will be five devices in the ECP3 range, with logic densities from 17,000 to 149,000 LUTs and with up to 586 user I/Os. Up to 6.8Mbit of embedded memory will also be available.
Apart from the serdes and LUTs, the parts will include dsp slices supporting 36 x 36 MAC operations, with each slice running at 500MHz.
Author
Graham Pitcher
Supporting Information
Websites
http://www.latticesemi.com
Companies
Lattice Semiconductor UK Ltd
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