08 June 2009

EEMBC launches MIPS busting benchmark

The Embedded Microprocessor Benchmark Consortium (EEMBC) has launched CoreMark 1.0, its first openly available benchmark. Traditionally, EEMBC has focused on specific embedded market segments to approximate the real world performance of embedded processors. But it claims CoreMark provides a starting point for measuring a processor's core performance and basic pipeline structure, allowing a wide range of devices to be evaluated.

The CoreMark workload contains several common algorithms, including matrix manipulation, linked list manipulation, state machine operation and cyclic redundancy check. According to EEMBC, these algorithms deliver a realistic mixture of read/write operations, integer operations and control operations.
Shay Gal-On, pictured, EEMBC's director of software engineering, said: "CoreMark is free, small and easily portable to most systems. However, unlike Dhrystone, CoreMark is not susceptible to a compiler's ability to optimise the work away and is governed by consistent run and reporting rules."
ARM is one of the first to announce support for CoreMark. Eric Schorn, vp of marketing for the company's processor division, said: "We believe that CoreMark represents a significant improvement on the current Dhrystone benchmarks. Combined with greater access to the results, this new benchmark should enable developers to obtain an unambiguous representation of processor performance enabling comparisons between competing processors to be made."
EEMBC has set up a website (www.coremark.org) for the distribution of CoreMark source code and for the publication of scores. CoreMark users are being encouraged by EEMBC to enter their scores and platform configurations on this website. It believes this publicly available list of scores will allow users to make quick comparisons between processors. An EEMBC EnergyBench enabled version of CoreMark is available to all EEMBC members and may also be licensed separately by non members.

Graham Pitcher

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